Abstract: A method and apparatus for improving performance and dynamic power in an electronic design are described. In one embodiment, the method comprises performing a place and routing operation for an integrated circuit (IC) design having a logic path; and performing a design optimization operation on the IC design, including upsizing drive strength along the logic path by substituting a 2-stage cell variation of a first cell having at least one 1-stage arc for another 2-stage cell along the logic path.