Abstract: A memory device generator for generating memory devices in a CAD environment, the generator composed of a library file containing predefined basic circuit components; memory array generation algorithm interacting with the library file for generating a variable-size memory array representation having a variable number of memory elements, and at least one redundant memory element; memory element selection circuit generation algorithm interacting with the library file for generating a memory element selection circuit to be associated with the memory array for selecting at least one memory element according to memory device address inputs.

Abstract: A memory device comprises an array of memory cells arranged in rows and columns, a plurality of gates for transmitting respective selection outputs of a row decoder to respective rows, a dummy column of dummy memory cells substantially identical to the memory cells, precharge means for precharging the columns and the dummy column at a precharge potential when no row is selected, and programming means for setting selected columns at respective programming potentials. The device comprises dummy memory cell preset means for presetting the dummy memory cells in a first logic state when no row is selected, dummy column programming means for setting the dummy column at a prescribed programming potential corresponding to a second logic state opposite to the first logic state, and first detector means for detecting that the dummy column has discharged from the precharge potential to the prescribed programming potential and for consequently enabling said plurality of gates.

Abstract: A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure, The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

Abstract: A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure. The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.