Abstract: According to an embodiment, a radio frequency delay line is described comprising a first conductor comprising a plurality of first inductors, a second conductor comprising a plurality of second inductors, wherein each of the plurality first inductors corresponds to a respective one of the plurality of second inductors and a plurality of inductor pairs, each inductor pair comprising a first inductor and the corresponding second inductor. For each of the plurality of inductor pairs, the first inductor and the corresponding second inductor are arranged so that an inductor area of the first inductor overlaps with an inductor area of the corresponding second inductor.

Abstract: According to an embodiment, a radio frequency delay line is described comprising a first conductor comprising a plurality of first inductors, a second conductor comprising a plurality of second inductors, wherein each of the plurality first inductors corresponds to a respective one of the plurality of second inductors and a plurality of inductor pairs, each inductor pair comprising a first inductor and the corresponding second inductor. For each of the plurality of inductor pairs, the first inductor and the corresponding second inductor are arranged so that an inductor area of the first inductor overlaps with an inductor area of the corresponding second inductor.

Abstract: Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The phase interpolator can be configured to receive digital representations of two or more distinct phase signals, and to interpolate the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal. The ring oscillator can be configured to receive the interpolated phase signal, to lock on to a frequency and a phase of the interpolated output phase signal, and to provide a filtered phase signal.

Abstract: Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The phase interpolator can be configured to receive digital representations of two or more distinct phase signals, and to interpolate the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal. The ring oscillator can be configured to receive the interpolated phase signal, to lock on to a frequency and a phase of the interpolated output phase signal, and to provide a filtered phase signal.

Abstract: In accordance with an embodiment, an oscillator includes a tank circuit and an oscillator core circuit having a plurality of cross-coupled compound transistors coupled to the tank circuit. Each of the plurality of compound transistors includes a bipolar transistor and a field effect transistor (FET) having a source coupled to a base of the bipolar transistor.

Abstract: In accordance with an embodiment, an oscillator includes a tank circuit and an oscillator core circuit having a plurality of cross-coupled compound transistors coupled to the tank circuit. Each of the plurality of compound transistors includes a bipolar transistor and a field effect transistor (FET) having a source coupled to a base of the bipolar transistor.

Abstract: This disclosure relates to a divide-by-N frequency divider system and frequency dividing method. The system includes a ring oscillator having M stages, where M is an integer, and a zero mean current component coupled to one or more of the stages to provide a zero mean current flow path.

Abstract: Apparatus and systems for synthesizing frequencies for use in a fast hopping wireless communications system. A frequency synthesizer comprises a plurality of oscillators with each oscillator having a first input coupled to a reference clock frequency signal, and a signal selector having a control signal input and a plurality of reference clock inputs with each reference clock input coupled to an output from an oscillator. Each oscillator produces a reference frequency that is a harmonic of a reference clock frequency of the reference clock frequency signal, and the signal selector couples a reference clock input to an output based on a control signal provided by the control signal input.

Abstract: This disclosure relates to a divide-by-N frequency divider system and frequency dividing method. The system includes a ring oscillator having M stages, where M is an integer, and a zero mean current component coupled to one or more of the stages to provide a zero mean current flow path.

Abstract: Apparatus and systems for synthesizing frequencies for use in a fast hopping wireless communications system. A frequency synthesizer comprises a plurality of oscillators with each oscillator having a first input coupled to a reference clock frequency signal, and a signal selector having a control signal input and a plurality of reference clock inputs with each reference clock input coupled to an output from an oscillator. Each oscillator produces a reference frequency that is a harmonic of a reference clock frequency of the reference clock frequency signal, and the signal selector couples a reference clock input to an output based on a control signal provided by the control signal input.

Abstract: An oscillator includes a first resonator circuit, a second resonator circuit coupled to the first resonator circuit and a reconfigurable network having a transconductance and coupled to at least one of the resonator circuits. Reconfiguration of the reconfigurable network with respect to the transconductance allows selection of one of multiple oscillation modes of the oscillator.

Abstract: An oscillator includes a first resonator circuit, a second resonator circuit coupled to the first resonator circuit and a reconfigurable network having a transconductance and coupled to at least one of the resonator circuits. Reconfiguration of the reconfigurable network with respect to the transconductance allows selection of one of multiple oscillation modes of the oscillator.