Abstract: The present disclosure relates to a floating-point computation device comprising: a first floating-point (FP) operation circuit (3202) comprising a first processing unit (3204) configured to perform a first operation on at least one input FP value (F1, F2) to generate a result; a first rounder circuit (3206); and a first control circuit (3302) configured to control a bit or byte length applied by a rounding operation of the first rounder circuit (3206), wherein the control circuit (3302) is configured to apply a first bit or byte length (BLA) if the result of the first operation is to be stored to an internal memory of the floating-point computation device to be used for a subsequent operation, and to apply a second bit or byte length (BLS), different to the first bit or byte length, if the result of the first operation is to be stored to an external memory.

Abstract: The present disclosure relates to a floating-point computation circuit comprising: an internal memory (104, 114) storing one or more floating-point values in a first format; status registers (124) defining a plurality of floating-point number format types associated with corresponding identifiers, each format type indicating at least a maximum size (BIS, MBB); and a load and store unit (108, 118) for loading floating-point values from and storing floating-point values to an external memory (120, 122), the load and store unit (108, 118) being configured: to receive, in relation with a first store operation, a first floating-point value from the internal memory (104, 114) and a first of said identifiers; and to convert the first floating-point value from the first format to a first external memory format having a maximum size (BIS, MBB) defined by the floating-point number format type designated by the first identifier.

Abstract: The present disclosure relates to a method of storing, by a load and store circuit or other processing means, a variable precision floating point value to a memory address of a memory, the method comprising: reducing the bit length of the variable precision floating point value to no more than a size limit, and storing the variable precision floating point value to one of a plurality of storage zones in the memory, each of the plurality of storage zones having a storage space equal to or greater than the size limit (MBB).

Abstract: The present disclosure relates to a method of storing, by a load and store circuit or other processing means, a variable precision floating point value to a memory address of a memory, the method comprising: reducing the bit length of the variable precision floating point value to no more than a size limit, and storing the variable precision floating point value to one of a plurality of storage zones in the memory, each of the plurality of storage zones having a storage space equal to or greater than the size limit (MBB).