Abstract: A power on reset circuit includes a threshold detector circuit. The threshold detector circuit includes a power supply voltage, a voltage comparator, first circuitry, second circuitry, and third circuitry. The voltage comparator has first and second input terminals, and an output terminal to provide a reset signal. The first circuitry is operable to convert the power supply voltage to a sensed current, and provides a positive temperature coefficient to the sensed current. The second circuitry is operable to generate, based on the sensed current, a temperature-dependent voltage corresponding to the power supply voltage and to couple the temperature-dependent voltage to the first input of the voltage comparator. The third circuitry is operable to generate, based on the sensed current, a reference voltage and to couple the reference voltage to the second input of the voltage comparator.

Abstract: A DC-DC converter includes an output power stage and a driver circuit. The output stage switches an input voltage to a switch node using a first transistor in response to a top-gate signal received at a top-gate node, and the switch node to ground using a second transistor in response to a bottom-gate signal received at a bottom-gate node. The driver circuit that provides the top- and bottom-gate signals in response to high- and low-side switch signals, respectively, activates the top-gate signal by actively regulating the top-gate node to a first voltage between a threshold voltage and a breakdown voltage of the first transistor using charge from the bottom-gate node, and activates the bottom-gate signal by actively regulating a second voltage provided to the bottom-gate node between a threshold voltage and a breakdown voltage of the second transistor using charge from the top-gate node.

Abstract: A serial data link (10) includes a transmitter (12) using a differential transmitter cell (20) to transmit data using differential signals and a receiver (14) using a differential receiver cell (22) to receive differential signals. When the transmitter (12) is in a power-down state, the differential signals from the differential transmitter cell (20) are set to an illegal state that is detected by the receiver cell (22). Upon detecting the illegal state, unnecessary circuitry in the receiver (14) is shut off or placed in a low power state to conserve energy. When data transmission resumes, the receiver cell (22) automatically restores power to its circuitry and resumes receiving data.

Abstract: A memory interface (20) for receiving memory signals individually synchronizes data signals to a delayed strobe signal in order to reduce the spread of the data signals prior to sampling. A delay is increased for an individual data signal if it transitions prior to the delayed strobe signal and the delay is decreased if the data signal transitions after the delayed strobe signal.

Abstract: A memory interface (20) for receiving memory signals individually synchronizes data signals to a delayed strobe signal in order to reduce the spread of the data signals prior to sampling. A delay is increased for an individual data signal if it transitions prior to the delayed strobe signal and the delay is decreased if the data signal transitions after the delayed strobe signal.

Abstract: A serial data link (10) includes a transmitter (12) using a differential transmitter cell (20) to transmit data using differential signals and a receiver (14) using a differential receiver cell (22) to receive differential signals. When the transmitter (12) is in a power-down state, the differential signals from the differential transmitter cell (20) are set to an illegal state that is detected by the receiver cell (22). Upon detecting the illegal state, unnecessary circuitry in the receiver (14) is shut off or placed in a low power state to conserve energy. When data transmission resumes, the receiver cell (22) automatically restores power to its circuitry and resumes receiving data.

Abstract: A high-impedance current source 100 having an enhanced compliance voltage. The current source 100 preferably has a means for generating a biasing current 105 and a first current mirror stage having a first transistor M6 coupled to a second transistor M1. A second current mirror stage having a third transistor M2 coupled to a fourth transistor M5 acts as a feedback circuit. A stabilization circuit having a fifth transistor M3 coupled to a sixth transistor M4 are also included. The stabilization circuit is coupled between the first and second current mirror stages and an output circuit having a seventh transistor M7 is connected to the stabilization circuit between the first and second current mirror stages. The current mirror circuit has a low compliance voltage, enhanced operating characteristics and enhanced dynamics which eliminate the need for OTAs.

Abstract: A high-impedance current source 100 having an enhanced compliance voltage. The current source 100 preferably has a means for generating a biasing current 105 and a first current mirror stage having a first transistor M6 coupled to a second transistor M1. A second current mirror stage having a third transistor M2 coupled to a fourth transistor M5 acts as a feedback circuit. A stabilization circuit having a fifth transistor M3 coupled to a sixth transistor M4 are also included. The stabilization circuit is coupled between the first and second current mirror stages and an output circuit having a seventh transistor M7 is connected to the stabilization circuit between the first and second current mirror stages. The current mirror circuit has a low compliance voltage, enhanced operating characteristics and enhanced dynamics which eliminate the need for OTAs.