Abstract: A materials handling vehicle includes a power unit, a load handling assembly and a positioning assistance system that provides assistance to an operator that is driving the vehicle. The assistance provided by the positioning assistance system includes at least one of an audible, tactile, or visual cue to indicate at least one of: a distance from the vehicle to a boundary object; or a heading of the vehicle with respect to the boundary object.

Abstract: A transit fare approach that offers a transit agency the ability to cap how many transit passes of a particular type in a given fare cycle would be equivalent of buying a discounted transit product (like a weekly pass, a bi-weekly pass, or a monthly pass). Once this equivalent is reached by a rider, the system automatically gives the rider the corresponding discount pass for free. The free pass remains activated and good for the remainder of the fare cycle. A software module provides a user app for the rider's mobile device and a controller app for a control unit of the transit agency, both of which operate in conjunction with each other to monitor the use of transit passes by the rider to determine when the rider qualifies for the fare cap-based free transit product and subsequently reward the rider with the free use of the appropriate transit product.

Abstract: Disclosed herein are computer-implemented method, system, and computer-program product (non-transitory computer-readable storage medium) embodiments for automatic test-pattern generation (ATPG) validation. An embodiment includes parsing an ATPG input, semantically analyzing the ATPG input, generating a first HDL model based on the semantic analysis, creating an HDL testbench based on the first HDL model, simulating an ATE test of a circuit structure, and outputting a validation result of the circuit structure, based on the simulating. In some embodiments, the parsing may include lexical and/or syntactic analysis. The HDL model may represent the circuit structure as functionally equivalent to the ATPG input, as determined based on the semantic analysis. In some embodiments, the ATPG input includes a cycle-based test pattern for a first block of the ATPG input, and the HDL testbench includes event-based test patterns that mimic given ATE behavior. The HDL model may be smaller in size than the ATPG input.

Abstract: A coating material for producing a coating includes 15 to 70 wt. % of at least one CH acidic compound, 4 to 40 wt. % of at least one vinylogous carbonyl compound, 0.1 to 15 wt. % of at least one latent-basic catalyst, 0.00001 to 10 wt. % of at least one light stabilizer, 0.00001 to 20 wt. % of at least one open time extender, 0.00001 to 20 wt. % of at least one pot life extender, 0.00001 to 70 wt. % of at least one of an inorganic pigment and an organic pigment, and 0.00001 to 25 wt. % of one at least one matting agent. Each wt. % of a respective ingredient is based on a total amount of the coating material.

Abstract: A coating material for producing a coating includes 10 to 70 wt. % of at least one CH acidic compound, 4 to 40 wt. % of at least one vinylogous carbonyl compound, 0.1 to 15 wt. % of at least one latent-basic catalyst, 0.00001 to 10 wt. % of at least one light stabilizer, 0.00001 to 20 wt. % of at least one open time extender, 0.00001 to 20 wt. % of at least one pot life extender, 0.00001 to 70 wt. % of at least one of an inorganic pigment and an organic pigment, and 0.1 to 40 wt. % of at least one corrosion protection agent. Each wt.

Abstract: Disclosed herein are computer-implemented method, system, and computer-program product (non-transitory computer-readable storage medium) embodiments for automatic test-pattern generation (ATPG) validation. An embodiment includes parsing an ATPG input, semantically analyzing the ATPG input, generating a first HDL model based on the semantic analysis, creating an HDL testbench based on the first HDL model, simulating an ATE test of a circuit structure, and outputting a validation result of the circuit structure, based on the simulating. In some embodiments, the parsing may include lexical and/or syntactic analysis. The HDL model may represent the circuit structure as functionally equivalent to the ATPG input, as determined based on the semantic analysis. In some embodiments, the ATPG input includes a cycle-based test pattern for a first block of the ATPG input, and the HDL testbench includes event-based test patterns that mimic given ATE behavior. The HDL model may be smaller in size than the ATPG input.

Abstract: A coating material for producing a coating includes 15 to 70 wt. % of at least one CH acidic compound, 4 to 40 wt. % of at least one vinylogous carbonyl compound, 0.1 to 15 wt. % of at least one latent-basic catalyst, 0.00001 to 10 wt. % of at least one light stabilizer, 0.00001 to 20 wt. % of at least one open time extender, and 0.00001 to 20 wt. % of at least one pot life extender. Each wt. % of a respective ingredient is based on a total amount of the coating material.

Abstract: A coating material for producing a coating includes 15 to 70 wt. % of at least one CH acidic compound, 4 to 40 wt. % of at least one vinylogous carbonyl compound, 0.1 to 15 wt. % of at least one latent-basic catalyst, 0.00001 to 10 wt. % of at least one light stabilizer, 0.00001 to 20 wt. % of at least one open time extender, 0.00001 to 20 wt. % of at least one pot life extender, 0.00001 to 70 wt. % of at least one of an inorganic pigment and an organic pigment, and 0.00001 to 25 wt. % of one at least one matting agent. Each wt. % of a respective ingredient is based on a total amount of the coating material.

Abstract: A coating material for producing a coating includes 10 to 70 wt. % of at least one CH acidic compound, 4 to 40 wt. % of at least one vinylogous carbonyl compound, 0.1 to 15 wt. % of at least one latent-basic catalyst, 0.00001 to 10 wt. % of at least one light stabilizer, 0.00001 to 20 wt. % of at least one open time extender, 0.00001 to 20 wt. % of at least one pot life extender, 0.00001 to 70 wt. % of at least one of an inorganic pigment and an organic pigment, and 0.1 to 40 wt. % of at least one corrosion protection agent. Each wt.

Abstract: A coating material for producing a coating includes 15 to 70 wt. % of at least one CH acidic compound, 4 to 40 wt. % of at least one vinylogous carbonyl compound, 0.1 to 15 wt. % of at least one latent-basic catalyst, 0.00001 to 10 wt. % of at least one light stabilizer, 0.00001 to 20 wt. % of at least one open time extender, and 0.00001 to 20 wt. % of at least one pot life extender. Each wt. % of a respective ingredient is based on a total amount of the coating material.

Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.

Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.

Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.

Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.