Patents by Inventor Andrea ENRICI

Andrea ENRICI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250219905
    Abstract: A network function distributed to and implemented by data centers, using a service communication proxy, may not be suitable for performing functions utilizing user-aware needs. A method for distributing a network function utilizing user-aware needs includes receiving user-aware information, calculating a network configuration for a plurality of network functions based on the user-aware information, and transmitting the network configuration to at least one connectivity agent.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Applicant: Nokia Solutions and Networks Oy
    Inventors: Bogdan USCUMLIC, Andrea ENRICI
  • Publication number: 20250217478
    Abstract: A software-defined network controller includes at least one processor and memory storing computer-executable instructions coupled to the at least one processor. The at least one processor is configured to execute the computer-executable instructions to cause the software-defined network controller to monitor performance characteristics of a machine learning trust manager, and evaluate the performance characteristics to determine whether the machine learning trust manager satisfies a performance threshold. In response to determining that the machine learning trust manager fails to satisfy the performance threshold, the processor deactivates the machine learning trust manager, and activates a deterministic trust manager in place of the machine learning trust manager.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Nokia Solutions and Networks Oy
    Inventors: Mouna KAROUI, Andrea ENRICI, Bogdan USCUMLIC
  • Publication number: 20250211496
    Abstract: According to an aspect, there is provided an apparatus configured to perform the following. The apparatus obtains one or more trained hidden Markov models whose hidden and observation states define expected future and current behavior of respective one or more operational parameters of a device over time. The apparatus receives one or more messages comprising values for the one or more operational parameters for successive time instances. The apparatus determines one or more sets of successive observation states based on the one or more messages. The apparatus determines one or more probability distributions of most probable paths through the one or more hidden Markov models using a Viterbi algorithm based on the one or more sets. The apparatus determines one or more values of a trust rate based at least on dispersion in the one or more probability distributions, and classifies the device as trusted/untrusted based thereon.
    Type: Application
    Filed: December 23, 2024
    Publication date: June 26, 2025
    Inventors: Mouna KAROUI, Andrea ENRICI
  • Patent number: 12316692
    Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network-based apparatus to: select at least a first bitstream from a central repository based on an indicator associated with a probability of concurrent, simultaneous or future execution of the first bitstream and a second bitstream at a network node, each of the first bitstream and the second bitstream including programming information for a device at the network node, the indicator being based on an embedding matrix mapping at least a subset of bitstreams in the central repository to an N-dimensional vector of real numbers; and output the first bitstream to the network node for storage and execution upon request.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: May 27, 2025
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Andrea Enrici, Faycal Ait Aoudia, Julien Lallet
  • Patent number: 12261779
    Abstract: In some examples, an apparatus for protocol independent deterministic transport of data in a time-sensitive network comprises a processor, a memory coupled to the processor, the memory configured to store program code executable by the processor, the program code comprising one or more instructions, whereby to cause the apparatus to receive synchronisation data from the network, the synchronisation data comprising a measure for a clock frequency supporting transport of deterministic data traffic over the network, receive multiple input packets, the input packets comprising deterministic data traffic and non-deterministic data traffic, and generate, from the multiple input packets and using the synchronisation data, a set of isochronous output packets comprising respective payloads and headers.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: March 25, 2025
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Bogdan Uscumlic, Andrea Enrici
  • Patent number: 12164426
    Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: December 10, 2024
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Andrea Enrici, Julien Lallet
  • Patent number: 12081636
    Abstract: A network device includes processing circuitry configured to cause the network device to: partition a flow graph for an application to generate a partitioned graph of nodes and edges, each of the nodes including computations mapped to an execution unit to execute at least a portion of the application, and each of the edges denoting communications between execution units; determine whether the partitioned graph is an irreducible graph; and schedule the computations and the communications for execution in response to determining that the partitioned graph is an irreducible graph.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: September 3, 2024
    Assignee: Nokia Solutions and Networks Oy
    Inventor: Andrea Enrici
  • Publication number: 20240236005
    Abstract: In some examples, an apparatus for protocol independent deterministic transport of data in a time-sensitive network comprises a processor, a memory coupled to the processor, the memory configured to store program code executable by the processor, the program code comprising one or more instructions, whereby to cause the apparatus to receive synchronisation data from the network, the synchronisation data comprising a measure for a clock frequency supporting transport of deterministic data traffic over the network, receive multiple input packets, the input packets comprising deterministic data traffic and non-deterministic data traffic, and generate, from the multiple input packets and using the synchronisation data, a set of isochronous output packets comprising respective payloads and headers.
    Type: Application
    Filed: December 1, 2023
    Publication date: July 11, 2024
    Inventors: Bogdan USCUMLIC, Andrea ENRICI
  • Publication number: 20240195742
    Abstract: Example embodiments disclose a method for avoiding deadlock in a network includes generating a finite state machine indicating possible routing decisions of incoming packets for a plurality of switches, analyzing the finite state machine, determining at least one memory overflow state based on the analyzing, generating at least one anti-deadlock rule in response to determining the at least one memory overflow state, and transmitting the at least one anti-deadlock rule to the plurality of switches.
    Type: Application
    Filed: December 8, 2022
    Publication date: June 13, 2024
    Applicant: Nokia Solutions and Networks Oy
    Inventor: Andrea Enrici
  • Patent number: 11979769
    Abstract: A programmable device includes a plurality of first partial reconfiguration slots, a plurality of transceivers and a second partial reconfiguration slot. The plurality of first partial reconfiguration slots are configured to execute one or more applications or network functions. The second partial reconfiguration slot is configured to route data traffic flows between the plurality of first partial reconfiguration slots and the plurality of transceivers.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: May 7, 2024
    Assignee: NOKIA SOLUTIONS AND NETWORKS OY
    Inventors: Bogdan Uscumlic, Andrea Enrici
  • Patent number: 11973674
    Abstract: A method for allocating resources of a field-programmable gate array (FPGA), the method comprising: deterministically estimating a maximum latency for executing a network service at the FPGA; determining that the maximum latency is less than a threshold latency value associated with the network service; outputting an acknowledgement indicating that the maximum latency is less than or equal to the threshold latency value; receiving confirmation that the FPGA has been selected to execute the network service within a threshold time period; and deterministically scheduling the resources of the FPGA for executing the network service in response to receiving the confirmation within the threshold time period.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: April 30, 2024
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Andrea Enrici, Bogdan Uscumlic, Julien Lallet
  • Publication number: 20230315634
    Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 5, 2023
    Applicant: Nokia Solutions and Networks Oy
    Inventors: Andrea ENRICI, Julien LALLET
  • Patent number: 11669452
    Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: June 6, 2023
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Andrea Enrici, Julien Lallet
  • Patent number: 11645120
    Abstract: A network device, including processing circuitry configured to determine a depth first search tree (DFST) based on a dependency graph included in a request to allocate memory bandwidth to a set of tasks, determine a set of groups of edges and nodes in the dependency graph based on the DFST, and allocate the memory bandwidth to the set of tasks by allocating the memory bandwidth to edges included in the set of groups of edges and nodes.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: May 9, 2023
    Assignee: Nokia Solutions and Networks Oy
    Inventor: Andrea Enrici
  • Patent number: 11579894
    Abstract: A device includes a plurality of reconfigurable resources, a bus, and a configurator. The bus interconnects the plurality of reconfigurable resources. The configurator is configured to deterministically compute a segmented interconnect configuration for the bus based on operational parameters associated with the device and operational constraints associated with program modules to be executed by the plurality of reconfigurable resources.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: February 14, 2023
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Andrea Enrici, Bogdan Uscumlic
  • Publication number: 20220345535
    Abstract: A network device includes processing circuitry configured to cause the network device to: partition a flow graph for an application to generate a partitioned graph of nodes and edges, each of the nodes including computations mapped to an execution unit to execute at least a portion of the application, and each of the edges denoting communications between execution units; determine whether the partitioned graph is an irreducible graph; and schedule the computations and the communications for execution in response to determining that the partitioned graph is an irreducible graph.
    Type: Application
    Filed: April 26, 2021
    Publication date: October 27, 2022
    Applicant: Nokia Solutions and Networks Oy
    Inventor: Andrea ENRICI
  • Publication number: 20220345930
    Abstract: A programmable device includes a plurality of first partial reconfiguration slots, a plurality of transceivers and a second partial reconfiguration slot. The plurality of first partial reconfiguration slots are configured to execute one or more applications or network functions. The second partial reconfiguration slot is configured to route data traffic flows between the plurality of first partial reconfiguration slots and the plurality of transceivers.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 27, 2022
    Applicant: Nokia Solutions and Networks Oy
    Inventors: Bogdan USCUMLIC, Andrea ENRICI
  • Publication number: 20220327063
    Abstract: At least one example embodiment provides a programmable logic device comprising: a plurality of reconfigurable slots programmed to execute functions requested by a plurality of users, the plurality of reconfigurable slots allocated among the plurality of users; a memory divided into a plurality of memory segments, the plurality of memory segments allocated among the plurality of reconfigurable slots; and a memory management circuit configured to dynamically adjust the plurality of memory segments based on at least one of activity or memory requirements of the plurality of reconfigurable slots.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 13, 2022
    Applicant: Nokia Solutions and Networks Oy
    Inventors: Andrea ENRICI, Julien LALLET
  • Publication number: 20220321403
    Abstract: A network device for managing network segmentation in a network infrastructure includes at least one processor, and at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the network device to receive a request to execute a distributed workload, the request including distributed workload information, compute a network configuration for the network infrastructure based on the distributed workload information and a current status of the network infrastructure, and configure a plurality of reconfigurable resources of a programmable device to execute the distributed workload based on the network configuration.
    Type: Application
    Filed: April 2, 2021
    Publication date: October 6, 2022
    Applicant: Nokia Solutions and Networks Oy
    Inventors: Andrea ENRICI, Bogdan USCUMLIC
  • Patent number: 11416399
    Abstract: A server includes a field programmable gate array (FPGA) partitioned into a set of partial reconfiguration (PR) slots and a memory that supports a set of logical buffers. A deterministic application request module (DARM) receives application requests to allocate the set of reconfiguration slots to one or more tenants and the one or more tenants configure the allocated reconfiguration slot to perform tasks. The DARM stores data associated with the application request in a first logical buffer from the set of logical buffers. A reconfiguration slot scheduling (RSS) module identifies a first reconfiguration slot from the set of reconfiguration slots and associates the first reconfiguration slot with the first logical buffer. A reconfiguration slot initialization (RSI) module reconfigures the first reconfiguration slot to perform the tasks based on the data stored in the first logical buffer.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: August 16, 2022
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Andrea Enrici, Bogdan Uscumlic