Abstract: A method for allocating resources of a field-programmable gate array (FPGA), the method comprising: deterministically estimating a maximum latency for executing a network service at the FPGA; determining that the maximum latency is less than a threshold latency value associated with the network service; outputting an acknowledgement indicating that the maximum latency is less than or equal to the threshold latency value; receiving confirmation that the FPGA has been selected to execute the network service within a threshold time period; and deterministically scheduling the resources of the FPGA for executing the network service in response to receiving the confirmation within the threshold time period.

Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.

Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.

Abstract: A network device, including processing circuitry configured to determine a depth first search tree (DFST) based on a dependency graph included in a request to allocate memory bandwidth to a set of tasks, determine a set of groups of edges and nodes in the dependency graph based on the DFST, and allocate the memory bandwidth to the set of tasks by allocating the memory bandwidth to edges included in the set of groups of edges and nodes.

Abstract: A device includes a plurality of reconfigurable resources, a bus, and a configurator. The bus interconnects the plurality of reconfigurable resources. The configurator is configured to deterministically compute a segmented interconnect configuration for the bus based on operational parameters associated with the device and operational constraints associated with program modules to be executed by the plurality of reconfigurable resources.

Abstract: A programmable device includes a plurality of first partial reconfiguration slots, a plurality of transceivers and a second partial reconfiguration slot. The plurality of first partial reconfiguration slots are configured to execute one or more applications or network functions. The second partial reconfiguration slot is configured to route data traffic flows between the plurality of first partial reconfiguration slots and the plurality of transceivers.

Abstract: A network device includes processing circuitry configured to cause the network device to: partition a flow graph for an application to generate a partitioned graph of nodes and edges, each of the nodes including computations mapped to an execution unit to execute at least a portion of the application, and each of the edges denoting communications between execution units; determine whether the partitioned graph is an irreducible graph; and schedule the computations and the communications for execution in response to determining that the partitioned graph is an irreducible graph.

Abstract: At least one example embodiment provides a programmable logic device comprising: a plurality of reconfigurable slots programmed to execute functions requested by a plurality of users, the plurality of reconfigurable slots allocated among the plurality of users; a memory divided into a plurality of memory segments, the plurality of memory segments allocated among the plurality of reconfigurable slots; and a memory management circuit configured to dynamically adjust the plurality of memory segments based on at least one of activity or memory requirements of the plurality of reconfigurable slots.

Abstract: A network device for managing network segmentation in a network infrastructure includes at least one processor, and at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the network device to receive a request to execute a distributed workload, the request including distributed workload information, compute a network configuration for the network infrastructure based on the distributed workload information and a current status of the network infrastructure, and configure a plurality of reconfigurable resources of a programmable device to execute the distributed workload based on the network configuration.

Abstract: A server includes a field programmable gate array (FPGA) partitioned into a set of partial reconfiguration (PR) slots and a memory that supports a set of logical buffers. A deterministic application request module (DARM) receives application requests to allocate the set of reconfiguration slots to one or more tenants and the one or more tenants configure the allocated reconfiguration slot to perform tasks. The DARM stores data associated with the application request in a first logical buffer from the set of logical buffers. A reconfiguration slot scheduling (RSS) module identifies a first reconfiguration slot from the set of reconfiguration slots and associates the first reconfiguration slot with the first logical buffer. A reconfiguration slot initialization (RSI) module reconfigures the first reconfiguration slot to perform the tasks based on the data stored in the first logical buffer.

Abstract: A network device, including processing circuitry configured to determine a depth first search tree (DFST) based on a dependency graph included in a request to allocate memory bandwidth to a set of tasks, determine a set of groups of edges and nodes in the dependency graph based on the DFST, and allocate the memory bandwidth to the set of tasks by allocating the memory bandwidth to edges included in the set of groups of edges and nodes.

Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.

Abstract: A device includes a plurality of reconfigurable resources, a bus, and a configurator. The bus interconnects the plurality of reconfigurable resources. The configurator is configured to deterministically compute a segmented interconnect configuration for the bus based on operational parameters associated with the device and operational constraints associated with program modules to be executed by the plurality of reconfigurable resources.

Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network-based apparatus to: select at least a first bitstream from a central repository based on an indicator associated with a probability of concurrent, simultaneous or future execution of the first bitstream and a second bitstream at a network node, each of the first bitstream and the second bitstream including programming information for a device at the network node, the indicator being based on an embedding matrix mapping at least a subset of bitstreams in the central repository to an N-dimensional vector of real numbers; and output the first bitstream to the network node for storage and execution upon request.

Abstract: A method for allocating resources of a field-programmable gate array (FPGA), the method comprising: deterministically estimating a maximum latency for executing a network service at the FPGA; determining that the maximum latency is less than a threshold latency value associated with the network service; outputting an acknowledgement indicating that the maximum latency is less than or equal to the threshold latency value; receiving confirmation that the FPGA has been selected to execute the network service within a threshold time period; and deterministically scheduling the resources of the FPGA for executing the network service in response to receiving the confirmation within the threshold time period.

Abstract: A server includes a field programmable gate array (FPGA) partitioned into a set of partial reconfiguration (PR) slots and a memory that supports a set of logical buffers. A deterministic application request module (DARM) receives application requests to allocate the set of reconfiguration slots to one or more tenants and the one or more tenants configure the allocated reconfiguration slot to perform tasks. The DARM stores data associated with the application request in a first logical buffer from the set of logical buffers. A reconfiguration slot scheduling (RSS) module identifies a first reconfiguration slot from the set of reconfiguration slots and associates the first reconfiguration slot with the first logical buffer. A reconfiguration slot initialization (RSI) module reconfigures the first reconfiguration slot to perform the tasks based on the data stored in the first logical buffer.