Patents by Inventor Andrea Irace

Andrea Irace has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220405867
    Abstract: A power distribution system comprises a first Smart Meter device for metering the power absorbed or yielded by a domestic utility, in which said first Smart Meter device is connected to a power distribution grid and dialogs in real time with other Smart Meters connected to other domestic utilities, in which said other Smart Meters are connected to the same power grid of said first Smart Meter device, in which said power distribution system is provided with multiple and comprehensive interconnections which connect said first Smart Meter device to the other Smart Meter nodes so as to form a network, in which the information on the energy production and consumption status of the network is available in each Smart Meter node of the network at all times, thus allowing the information on the energy status of the network to be instantaneously available to an operator of the power grid by querying a single Smart Meter among those present in the network.
    Type: Application
    Filed: November 17, 2020
    Publication date: December 22, 2022
    Inventors: Andrea Irace, Francesco Arena
  • Patent number: 8685849
    Abstract: A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: April 1, 2014
    Assignee: Siliconix Technology C. V. IR
    Inventors: Andrea Irace, Giovanni Breglio, Paolo Spirito, Andrea Bricconi, Diego Raffo, Luigi Merlin
  • Patent number: 8274128
    Abstract: A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: September 25, 2012
    Assignee: Siliconix Technology C. V. IR
    Inventors: Andrea Irace, Giovanni Breglio, Paolo Spirito, Andrea Bricconi, Diego Raffo, Luigi Merlin
  • Publication number: 20090224355
    Abstract: A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region.
    Type: Application
    Filed: March 24, 2008
    Publication date: September 10, 2009
    Applicant: SILICONIX TECHNOLOGY C. V. IR
    Inventors: Andrea Irace, Giovanni Breglio, Paolo Spirito, Andrea Bricconi, Diego Raffo, Luigi Merlin