Abstract: An optimization engine identifies an infeasible node in a tree data structure that corresponds to a programming model, and computes a fake objective value for the infeasible node. The optimization engine then updates a branching variable pseudocost using the fake objective value. Next, the optimization engine uses multiple branching variable pseudocosts corresponding to multiple branching variable candidates in order to select one of the branching variable candidates. In turn, the optimization engine branches to the corresponding branch of the selected branching variable.

Abstract: An optimization engine identifies an infeasible node in a tree data structure that corresponds to a programming model, and computes a fake objective value for the infeasible node. The optimization engine then updates a branching variable pseudocost using the fake objective value. Next, the optimization engine uses multiple branching variable pseudocosts corresponding to multiple branching variable candidates in order to select one of the branching variable candidates. In turn, the optimization engine branches to the corresponding branch of the selected branching variable.

Abstract: An optimization engine identifies an infeasible node in a tree data structure that corresponds to a programming model, and computes a fake objective value for the infeasible node. The optimization engine then updates a branching variable pseudocost using the fake objective value. Next, the optimization engine uses multiple branching variable pseudocosts corresponding to multiple branching variable candidates in order to select one of the branching variable candidates. In turn, the optimization engine branches to the corresponding branch of the selected branching variable.

Abstract: An optimization engine identifies an infeasible node in a tree data structure that corresponds to a programming model, and computes a fake objective value for the infeasible node. The optimization engine then updates a branching variable pseudocost using the fake objective value. Next, the optimization engine uses multiple branching variable pseudocosts corresponding to multiple branching variable candidates in order to select one of the branching variable candidates. In turn, the optimization engine branches to the corresponding branch of the selected branching variable.

Abstract: An embodiment of the invention relates to a T-switch for connecting first, second and third lines and comprising an input section in turn including first, second and third input pass transistors, each connecting a respective line with a first internal node of the T-switch, an output section in turn including first, second and third output pass transistors, each connecting a respective line with a second internal node of the T-switch, and a single buffer stage connected to a first and a second voltage reference and inserted between the first and second internal node.

Abstract: A switch block suitable to realize the connection between interconnection lines connected thereto of the type comprising at least a switching block connected to the interconnection lines and including at least a buffer stage in turn connected to a plurality of transistors. The switch block comprises a decoding stage inserted between a plurality of SRAM cells and respective control terminals of the plurality of transistors of the switching block.

Abstract: A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.

Abstract: An embodiment of the invention relates to a T-switch for connecting first, second and third lines and comprising an input section in turn including first, second and third input pass transistors, each connecting a respective line with a first internal node of the T-switch, an output section in turn including first, second and third output pass transistors, each connecting a respective line with a second internal node of the T-switch, and a single buffer stage connected to a first and a second voltage reference and inserted between the first and second internal node.

Abstract: A digital embedded architecture, includes a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor, structured to implement a Very Long Instruction Word elaboration mode by a general purpose hardwired computational logic, and an additional data elaboration channel comprising a reconfigurable function unit based on a pipelined array of configurable look-up table based cells controlled by a special purpose control unit, thus easing the elaboration of critical kernels algorithms.

Abstract: A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.

Abstract: An optimized architecture to implement connections between logic blocks and routing lines in reconfigurable gate arrays including connection blocks to connect inputs and outputs of different logic elements by means of connection wires, each connection block including a single line of pass transistor switches; and a decoding stage to drive the pass transistor switch.

Abstract: A portable unit for detecting a position with respect to a reference, particularly for substantially shielded environments, comprising a suitable power supply element. The unit comprises a control and processing processor, a device for three-dimensional orientation with respect to geographical references, at least one accelerometer, a screen, a memory component and respective data input and output interfaces. The processor is preset by the user by means of the input interface and is adapted to process instantaneously the data supplied during use by the orientation device and by the at least one accelerometer, displaying the processing on the screen and storing it in the memory component.

Abstract: A switch block suitable to realize the connection between interconnection lines connected thereto of the type comprising at least a switching block connected to the interconnection lines and including at least a buffer stage in turn connected to a plurality of transistors. The switch block comprises a decoding stage inserted between a plurality of SRAM cells and respective control terminals of the plurality of transistors of the switching block.

Abstract: A digital embedded architecture, includes a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor, structured to implement a Very Long Instruction Word elaboration mode by a general purpose hardwired computational logic, and an additional data elaboration channel comprising a reconfigurable function unit based on a pipelined array of configurable look-up table based cells controlled by a special purpose control unit, thus easing the elaboration of critical kernels algorithms.

Abstract: An optimised architecture to implement connections between logic blocks and routing lines in reconfigurable gate arrays including connection blocks to connect inputs and outputs of different logic elements by means of connection wires, each connection block including a single line of pass transistor switches; and a decoding stage to drive the pass transistor switch.

Abstract: A Pharmaceutical composition in a form suitable for parenteral administration comprising a solution of the glycine antagonist (E)-3-[2-phenylcarbamoyl) ethenyl]-4,6-dichloroindole-2-carboxylic, acid or a physiologically acceptable salt thereof, in an isotonic sugar solution containing a water miscible organic solvent for the compound, said formulation having a pH within the range of 7 to 9.

Abstract: A pharmaceutical composition is disclosed in a form suitable for parenteral administration, comprising a solution of the glycine antagonist, (E)-3-?2-(phenylcarbamoyl) ethenyl!-4,6-dichloroindole-2-carboxylic acid, or a physiologically acceptable salt thereof, in an isotonic sugar solution containing a water miscible organic solvent for the compound, said formulation having a pH within the range of 7 to 9.