Abstract: A latch is provided. The latch includes a plurality of storage nodes including a plurality of data storage nodes configured to store a data bit having one of two states and a plurality of complementary data storage nodes configured to store a complement of the data bit. The latch includes a plurality of supply voltage multi-dependency stages respectively corresponding to the plurality of storage nodes. Each supply voltage multi-dependency stage has an output coupled to a storage node and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes. The supply voltage multi-dependency stage is configured to cause a state of the data bit stored in the storage node to change from a first state to a second state in response a change in both states of two data bits respectively stored in the at least two other storage nodes.

Abstract: A latch is provided. The latch includes a plurality of storage nodes including a plurality of data storage nodes configured to store a data bit having one of two states and a plurality of complementary data storage nodes configured to store a complement of the data bit. The latch includes a plurality of supply voltage multi-dependency stages respectively corresponding to the plurality of storage nodes. Each supply voltage multi-dependency stage has an output coupled to a storage node and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes. The supply voltage multi-dependency stage is configured to cause a state of the data bit stored in the storage node to change from a first state to a second state in response a change in both states of two data bits respectively stored in the at least two other storage nodes.

Abstract: According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.

Abstract: According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.

Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.