Patents by Inventor Andrea MASCHERONI

Andrea MASCHERONI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9442856
    Abstract: A data processing apparatus has data processing circuitry for performing data processing operations on data, and a hierarchical cache structure for storing at least a subset of the data for access by the data processing circuitry. The hierarchical cache structure has first and second level caches, and data evicted from the first level cache is routed to the second level cache under the control of second level cache access control circuitry. Cache maintenance circuitry performs a cache maintenance operation in both the first level cache and the second level cache. The access control circuitry is responsive to maintenance indication data to modify the eviction handling operation performed in response to the evicted data, so as to cause the required cache maintenance for the second level cache to be incorporated within the eviction handling operation.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: September 13, 2016
    Assignee: ARM Limited
    Inventors: Gilles Eric Grandou, Philippe Jean-Pierre Raphalen, Andrea Mascheroni
  • Publication number: 20150269079
    Abstract: A data processing apparatus has data processing circuitry for performing data processing operations on data, and a hierarchical cache structure for storing at least a subset of the data for access by the data processing circuitry. The hierarchical cache structure has first and second level caches, and data evicted from the first level cache is routed to the second level cache under the control of second level cache access control circuitry. Cache maintenance circuitry performs a cache maintenance operation in both the first level cache and the second level cache. The access control circuitry is responsive to maintenance indication data to modify the eviction handling operation performed in response to the evicted data, so as to cause the required cache maintenance for the second level cache to be incorporated within the eviction handling operation.
    Type: Application
    Filed: June 5, 2015
    Publication date: September 24, 2015
    Inventors: Gilles Eric GRANDOU, Philippe Jean-Pierre RAPHALEN, Andrea MASCHERONI
  • Patent number: 9081685
    Abstract: A data processing apparatus has data processing circuitry for performing data processing operations on data, and a hierarchical cache structure for storing at least a subset of the data for access by the data processing circuitry. The hierarchical cache structure has first and second level caches, and data evicted from the first level cache is routed to the second level cache under the control of second level cache access control circuitry. Cache maintenance circuitry performs a cache maintenance operation in both the first level cache and the second level cache. The access control circuitry is responsive to maintenance indication data to modify the eviction handling operation performed in response to the evicted data, so as to cause the required cache maintenance for the second level cache to be incorporated within the eviction handling operation.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: July 14, 2015
    Assignee: ARM Limited
    Inventors: Gilles Eric Grandou, Philippe Jean-Pierre Raphalen, Andrea Mascheroni
  • Publication number: 20140201447
    Abstract: A data processing apparatus has data processing circuitry for performing data processing operations on data, and a hierarchical cache structure for storing at least a subset of the data for access by the data processing circuitry. The hierarchical cache structure has first and second level caches, and data evicted from the first level cache is routed to the second level cache under the control of second level cache access control circuitry. Cache maintenance circuitry performs a cache maintenance operation in both the first level cache and the second level cache. The access control circuitry is responsive to maintenance indication data to modify the eviction handling operation performed in response to the evicted data, so as to cause the required cache maintenance for the second level cache to be incorporated within the eviction handling operation.
    Type: Application
    Filed: January 15, 2013
    Publication date: July 17, 2014
    Applicant: ARM LIMITED
    Inventors: Gilles Eric GRANDOU, Philippe Jean-Pierre RAPHALEN, Andrea MASCHERONI