Patents by Inventor Andrea Mitchell
Andrea Mitchell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9269669Abstract: A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.Type: GrantFiled: February 23, 2012Date of Patent: February 23, 2016Assignee: Infineon Technologies AGInventors: Johann Helneder, Markus Schwerd, Thomas Goebel, Andrea Mitchell, Heinrich Koerner, Martina Hommel
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Patent number: 8367514Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.Type: GrantFiled: January 29, 2010Date of Patent: February 5, 2013Assignee: Infineon Technologies AGInventors: Thomas Goebel, Johann Helneder, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck, Holger Torwesten
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Patent number: 8228090Abstract: A system for testing and a method for making a semiconductor device is disclosed. A preferred embodiment includes a conductor overlying a dielectric layer. The conductor is coupled to a first test pad via a first conducting line and to a second test pad via a second conducting line.Type: GrantFiled: April 11, 2011Date of Patent: July 24, 2012Assignee: Infineon Technologies AGInventors: Andreas Martin, Karl-Henrik Rydén, Andrea Mitchell
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Publication number: 20120149168Abstract: A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.Type: ApplicationFiled: February 23, 2012Publication date: June 14, 2012Inventors: Johann Helneder, Markus Schwerd, Thomas Goebel, Andrea Mitchell, Heinrich Koerner, Martina Hommel
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Publication number: 20110187382Abstract: A system for testing and a method for making a semiconductor device is disclosed. A preferred embodiment includes a conductor overlying a dielectric layer. The conductor is coupled to a first test pad via a first conducting line and to a second test pad via a second conducting line.Type: ApplicationFiled: April 11, 2011Publication date: August 4, 2011Inventors: Andreas Martin, Karl-Henrik Rydén, Andrea Mitchell
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Patent number: 7964494Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.Type: GrantFiled: September 18, 2009Date of Patent: June 21, 2011Assignee: Infineon Technologies AGInventors: Stefan Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck
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Patent number: 7948259Abstract: A system for testing and a method for making a semiconductor device is disclosed. A preferred embodiment includes a conductor overlying a dielectric layer. The conductor is coupled to a first test pad via a first conducting line and to a second test pad via a second conducting line.Type: GrantFiled: October 5, 2010Date of Patent: May 24, 2011Assignee: Infineon Technologies AGInventors: Andreas Martin, Karl-Henrik Rydén, Andrea Mitchell
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Publication number: 20110037490Abstract: A system for testing and a method for making a semiconductor device is disclosed. A preferred embodiment includes a conductor overlying a dielectric layer. The conductor is coupled to a first test pad via a first conducting line and to a second test pad via a second conducting line.Type: ApplicationFiled: October 5, 2010Publication date: February 17, 2011Inventors: Andreas Martin, Karl-Henrik Rydén, Andrea Mitchell
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Patent number: 7825679Abstract: A system for testing and a method for making a semiconductor device is disclosed. A preferred embodiment includes a conductor overlying a dielectric layer. The conductor is coupled to a first test pad via a first conducting line and to a second test pad via a second conducting line.Type: GrantFiled: April 6, 2009Date of Patent: November 2, 2010Assignee: Infineon Technologies AGInventors: Andreas Martin, Karl-Henrik Rydén, Andrea Mitchell
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Publication number: 20100253380Abstract: A system for testing and a method for making a semiconductor device is disclosed. A preferred embodiment includes a conductor overlying a dielectric layer. The conductor is coupled to a first test pad via a first conducting line and to a second test pad via a second conducting line.Type: ApplicationFiled: April 6, 2009Publication date: October 7, 2010Inventors: Andreas Martin, Karl-Henrik Ryden, Andrea Mitchell
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Publication number: 20100129977Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.Type: ApplicationFiled: January 29, 2010Publication date: May 27, 2010Inventors: Thomas Goebel, Johann Helneder, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck, Holger Torwesten
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Patent number: 7692266Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.Type: GrantFiled: March 3, 2006Date of Patent: April 6, 2010Assignee: Infineon Technologies A.G.Inventors: Thomas Goebel, Johann Helneder, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck, Holger Torwesten
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Publication number: 20100007027Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.Type: ApplicationFiled: September 18, 2009Publication date: January 14, 2010Inventors: Stephen Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck
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Patent number: 7619309Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.Type: GrantFiled: February 9, 2006Date of Patent: November 17, 2009Assignee: Infineon Technologies AGInventors: Stefan Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Kôrner, Andrea Mitchell, Markus Schwerd, Martin Seck
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Publication number: 20060222760Abstract: A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.Type: ApplicationFiled: March 21, 2006Publication date: October 5, 2006Inventors: Johann Helneder, Markus Schwerd, Thomas Goebel, Andrea Mitchell, Heinrich Koerner, Martina Hommel
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Publication number: 20060214265Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.Type: ApplicationFiled: March 3, 2006Publication date: September 28, 2006Inventors: Thomas Goebel, Johann Helneder, Heinrich Korner, Andrea Mitchell, Markus Schwerd, Martin Seck, Holger Torwesten
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Publication number: 20060192289Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.Type: ApplicationFiled: February 9, 2006Publication date: August 31, 2006Inventors: Stefan Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Korner, Andrea Mitchell, Markus Schwerd, Martin Seck