Abstract: A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sector. A main read row decoder is connected to the main read wordlines, and a main program row decoder connected to the main program wordlines. Main read bitlines and main program bitlines are connected to the local bitlines in each sector. A main read column decoder is connected to the main read bitlines, and a main program column decoder is connected to the main program wordlines. A read address bus is connected to the main read row decoder and to the main read column decoder for providing an address thereto. A program address bus is connected to the main read column decoder and to the main program row decoder for providing an address thereto.

Abstract: A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sector. A main read row decoder is connected to the main read wordlines, and a main program row decoder connected to the main program wordlines. Main read bitlines and main program bitlines are connected to the local bitlines in each sector. A main read column decoder is connected to the main read bitlines, and a main program column decoder is connected to the main program wordlines. A read address bus is connected to the main read row decoder and to the main read column decoder for providing an address thereto. A program address bus is connected to the main read column decoder and to the main program row decoder for providing an address thereto.

Abstract: A memory array is divided, at the design stage, into a plurality of elementary sectors; depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors of desired size and number; a correlating unit memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address is supplied to the correlating unit which provides for addressing the elementary sectors associated with the addressed composite sector on the basis of the memorized correlation table.

Abstract: A memory array is divided, at the design stage, into a plurality of elementary sectors; depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors of desired size and number; a correlating unit memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address is supplied to the correlating unit which provides for addressing the elementary sectors associated with the addressed composite sector on the basis of the memorized correlation table.

Abstract: A memory device having a memory array, a row decoding unit, a column decoding unit, and a control unit; the memory array presents global bit lines extending along the whole of the array and connected to respective local bit lines, one for each of the sectors; a switch is provided between the global bit lines and each respective local bit line to selectively connect a selected global bit line and only one of the associated local bit lines; and the switches are controlled by local decoding units over control lines, to address the sectors independently and so perform operations (read, erase, write) simultaneously in two different sectors in different rows and columns.