Abstract: The invention relates to a circuit architecture for processing multi-channel frames of broadband synchronous digital signals, in particular signals of the SONET/SDH standard. The circuit includes an input portion and an output portion. It also contains at least one modular component adapted to process frames comprising a single channel and connectable modularly to N further identical components corresponding to the number of frame channels.

Abstract: A method of reducing power consumption of an electric circuit having a primary supply voltage and first and second circuit blocks is discussed. The method includes determining for the first circuit block an operation time for a first critical path of the first circuit block and determining for the second circuit block an operation time of a second critical path of the second circuit block. From those operation times, the method determines that the operation time of the first critical path is faster than the operation time of the second critical path. The method then creates a first supply voltage for the first circuit block that is less than the primary supply voltage in response to determining that the operation time of the first critical path is faster than the operation time of the second critical path.