Abstract: An electronic device, a method, and a chipset for receiving global navigation satellite system (GNSS) signals are provided. An input/output (I/O) mixer including a first multiplier and a second multiplier downconverts a modulated radio frequency wave to an intermediate frequency. The modulated radio frequency wave is input to first inputs of the first multiplier and the second multiplier, and where an in-phase signal, from a first digital to analog converter (DAC), and a quadrature phase signal, from a second DAC, are input to second inputs of the first multiplier and the second multiplier, respectively. A mixer imbalance between the first mixer and the second mixer is reduced using direct current (DC) bias voltages from the first DAC and the second DAC. The DC bias voltages are determined based on a first and second DAC codes of the first and second DACs. The downconverted modulated radio frequency wave is filtered.

Abstract: An electronic device, a method, and a chipset for receiving global navigation satellite system (GNSS) signals are provided. An input/output (I/O) mixer including a first multiplier and a second multiplier downconverts a modulated radio frequency wave to an intermediate frequency. The modulated radio frequency wave is input to first inputs of the first multiplier and the second multiplier, and where an in-phase signal, from a first digital to analog converter (DAC), and a quadrature phase signal, from a second DAC, are input to second inputs of the first multiplier and the second multiplier, respectively. A mixer imbalance between the first mixer and the second mixer is reduced using direct current (DC) bias voltages from the first DAC and the second DAC. The DC bias voltages are determined based on a first and second DAC codes of the first and second DACs. The downconverted modulated radio frequency wave is filtered.

Abstract: An electronic device, a method, and a chipset for receiving global navigation satellite system (GNSS) signals are provided. The electronic device includes a processor configured to: downconvert, by an input/output (I/O) mixer including a first multiplier and a second multiplier, a modulated radio frequency wave to an intermediate frequency, where the modulated radio frequency wave is input to first inputs of the first multiplier and the second multiplier, and where an in-phase signal and a quadrature phase signal based on a square wave are input to second inputs of the first multiplier and the second multiplier, respectively; filter the downconverted modulated radio frequency wave; and convert the filtered downconverted modulated radio frequency wave to a digital signal.

Abstract: An electronic device, a method, and a chipset for receiving global navigation satellite system (GNSS) signals are provided. The electronic device includes a processor configured to: downconvert, by an input/output (I/O) mixer including a first multiplier and a second multiplier, a modulated radio frequency wave to an intermediate frequency, where the modulated radio frequency wave is input to first inputs of the first multiplier and the second multiplier, and where an in-phase signal and a quadrature phase signal based on a square wave are input to second inputs of the first multiplier and the second multiplier, respectively; filter the downconverted modulated radio frequency wave; and convert the filtered downconverted modulated radio frequency wave to a digital signal.

Abstract: A method and apparatus is provided. The apparatus a processor configured to generate a first square wave, generate a second square wave, wherein the first square wave and the second square wave are driven by a reference frequency oscillator, modulate a radio frequency wave with the first square wave, downconvert the modulated radio frequency wave to an intermediate frequency, filter the downconverted modulated radio frequency wave, convert the filtered downconverted modulated radio frequency wave to a digital signal, and integrate the digital signal.

Abstract: A method and apparatus is provided. The apparatus a processor configured to generate a first square wave, generate a second square wave, wherein the first square wave and the second square wave are driven by a reference frequency oscillator, modulate a radio frequency wave with the first square wave, downconvert the modulated radio frequency wave to an intermediate frequency, filter the downconverted modulated radio frequency wave, convert the filtered downconverted modulated radio frequency wave to a digital signal, and integrate the digital signal.