Abstract: A dynamically reconfigurable universal transmitter system is disclosed herein. The electronic device includes multiple transmitter resources for generating transmission signals, an output bus; and an antenna summer coupled to the output bus. The output bus is selectively coupled to the plurality of transmitter resources and it selectively receives transmission signals from the plurality of transmission resources. The antenna summer stores transmission signals received on the output bus.

Abstract: A dynamically reconfigurable universal transmitter system is disclosed herein. The electronic device includes multiple transmitter resources for generating transmission signals, an output bus; and an antenna summer coupled to the output bus. The output bus is selectively coupled to the plurality of transmitter resources and it selectively receives transmission signals from the plurality of transmission resources. The antenna summer stores transmission signals received on the output bus.

Abstract: A dynamically reconfigurable universal transmitter system is disclosed herein. The electronic device includes multiple transmitter resources for generating transmission signals, an output bus, and an antenna summer coupled to the output bus. The output bus is selectively coupled to the plurality of transmitter resources and it selectively receives transmission signals from the plurality of transmission resources. The antenna summer stores transmission signals received on the output bus.

Abstract: A dynamically reconfigurable universal transmitter system is disclosed herein. The electronic device includes multiple transmitter resources for generating transmission signals, an output bus, and an antenna summer coupled to the output bus. The output bus is selectively coupled to the plurality of transmitter resources and it selectively receives transmission signals from the plurality of transmission resources. The antenna summer stores transmission signals received on the output bus.

Abstract: A main memory scheduler includes a store, and stores therein requests for accessing main memory (such as a read request, a write request, or a refresh request). Normally, the main memory scheduler issues requests from the store to the main memory in an order different from the order in which the requests are received, for example, to avoid bank conflicts. In this example, the main memory scheduler issues a first request to a first memory bank that is not coincident with (and in case of dependent banks, not adjacent to) a second memory bank (that is being currently accessed) prior to issuing a second request to a memory bank that is coincident with the (or adjacent to) second memory bank. Moreover, the main memory scheduler issues a refresh request prior to issuing a read request or a write request even if the refresh request was most recently received, thereby to prioritize the refresh request ahead of read and write requests.

Abstract: A dynamically reconfigurable universal transmitter system is disclosed herein. The electronic device includes multiple transmitter resources for generating transmission signals, an output bus, and an antenna summer coupled to the output bus. The output bus is selectively coupled to the plurality of transmitter resources and it selectively receives transmission signals from the plurality of transmission resources. The antenna summer stores transmission signals received on the output bus.

Abstract: A bank conflict detector compares at least a portion of a current address signal (i.e. an address signal generated by a request currently issued to main memory) with a corresponding portion of a to-be-issued memory address signal, to determine if a bank conflict exists. Specifically, in one embodiment, the bank conflict detector includes a number of exclusive OR gates that receive as inputs the two addresses to be compared, and generate an output (also called “XOR result”) that is compared with predetermined patterns to determine if a bank conflict exists. For example, if the bank conflict detector finds that the XOR result is 0 (zero) then the two addresses access the same bank. The bank conflict detector also the XOR result with patterns that are formed by a number of consecutive 1s in the least significant bits and a number of consecutive 0s in the most significant bits. If no match, then the bank conflict detector determines that no bank conflict exists.

Abstract: A main memory scheduler includes a store, and stores therein requests for accessing main memory (such as a read request, a write request, or a refresh request). Normally, the main memory scheduler issues requests from the store to the main memory in an order different from the order in which the requests are received, for example, to avoid bank conflicts. In this example, the main memory scheduler issues a first request to a first memory bank that is not coincident with (and in case of dependent banks, not adjacent to) a second memory bank (that is being currently accessed) prior to issuing a second request to a memory bank that is coincident with the (or adjacent to) second memory bank. Moreover, the main memory scheduler issues a refresh request prior to issuing a read request or a write request even if the refresh request was most recently received, thereby to prioritize the refresh request ahead of read and write requests.