Abstract: Method for checking a circuit layout for a semiconductor apparatus, including: (a) recording a circuit layout which has been created; (b) carrying out a test to determine whether predeterminable conditions are satisfied in the circuit layout; (c) if at least one predeterminable condition is not satisfied, (c1) determining position data for the at least one circuit part of the circuit layout for which at least one predeterminable condition is not satisfied; and (d) carrying out a simulation for the at least one circuit part determined in step (c), in order to obtain a simulation result.

Abstract: A memory device includes a memory module, a control unit and a bus connected to the memory module and the control unit. In an accessing operation of the memory module via bus, the control unit applies a first command which causes high power consumption in the memory module, to the memory module via part of the bus only.

Abstract: The present invention provides a wafer handling device having a base plate (G; G′), which has a first and a second supporting surface for a respective wafer (W1, W2) to be laid on; and a fixing device (K1, K2, S; K1′, K2′, S′) for the detachable fixing of the respective wafer (W1, W2) on the first and second supporting surface; the fixing device (K1, K2, S; K1′, K2′, S′) being configured in such a way that it contacts the respective wafer (W1, W2) only in the outer edge region of the side facing away from the supporting surface.

Abstract: A method for driving a plurality of circuit units to be controlled includes applying a control signal to a control signal connection unit and an activation signal to an activation connection unit. A hold signal is the generated on the in response to the activation signal. This hold signal is combined with the control signal to obtain a modified control signal, which is then made available at an output.

Abstract: The present invention provides a wafer handling device having a base plate (G; G′), which has a first and a second supporting surface for a respective wafer (W1, W2) to be laid on; and a fixing device (K1, K2, S; K1′, K2′, S′) for the detachable fixing of the respective wafer (W1, W2) on the first and second supporting surface; the fixing device (K1, K2, S; K1′, K2′, S′) being configured in such a way that it contacts the respective wafer (W1, W2) only in the outer edge region of the side facing away from the supporting surface.