Abstract: A semiconductor component includes an asymmetric transistor having two lightly doped drain regions (1300, 1701), a channel region (1702), a source region (1916) located within the channel region (1702), a drain region located outside the channel region (1702), a dielectric structure (1404) located over at least one of the two lightly doped drain regions (1300, 1701), two gate electrodes (1902, 1903) located at opposite sides of the dielectric structure (1404), a drain electrode (1901) overlying the drain region (1915), and a source electrode (1904) overlying the source region (1916). The semiconductor component also includes another transistor having an emitter electrode (122) located between a base electrode (121) and a collector electrode (123) where the base electrode (121) is formed over a dielectric structure (1405).

Abstract: An insulated gate semiconductor device (10) has a double spacer gate structure (45). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate oxide (23) is then formed over the major surface (12) adjacent the sidewalls (22). A first polysilicon layer (24) is deposited on the gate oxide (23) and the stack. The first polysilicon layer (24) is etched to form a first conductive spacer (32) of the gate structure (45). A second polysilicon layer (44) is deposited on first spacer (32) and the stack. The second polysilicon layer (44) is then etched to form a second conductive spacer (46) of the gate structure (45). Because the double spacer gate structure (45) is formed without relying on photolithographic techniques, its size is smaller than the size of a gate structure formed using conventional photolithography.

Abstract: A semiconductor component includes an asymmetric transistor having two lightly doped drain regions (1300, 1701), a channel region (1702), a source region (1916) located within the channel region (1702), a drain region located outside the channel region (1702), a dielectric structure (1404) located over at least one of the two lightly doped drain regions (1300, 1701), two gate electrodes (1902, 1903) located at opposite sides of the dielectric structure (1404), a drain electrode (1901) overlying the drain region (1915), and a source electrode (1904) overlying the source region (1916). The semiconductor component also includes another transistor having an emitter electrode (122) located between a base electrode (121) and a collector electrode (123) where the base electrode (121) is formed over a dielectric structure (1405).

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60,97) that can be used to transport electrical signals across the device (10).

Abstract: A semiconductor device (10) is formed in a pedestal structure (16) overlying an epitaxial layer (12) and a semiconductor substrate (11). The semiconductor device (10) includes a doped region (13) that forms a PN junction with the epitaxial layer (12). The semiconductor device (10) also includes a dielectric layer (22) that has an opening (23) that exposes a portion of the doped region (13) and an opening (24) that exposes a portion of the epitaxial layer (12). The openings (23, 24) are filled with a conductive material (36, 37) to provide contacts (100, 101). Due to the presence of the PN junction, the contacts (100, 101) are capacitively coupled to each other.

Abstract: A circuit and method protect a transistor (68, 70) from damage when controlling an input signal (V.sub.PROG) that exceeds a gate to channel stress voltage of the transistor. A small, low current protection transistor (64, 66) is serially coupled to the gate electrode of the transistor being protected. The gate of the protection transistor is biased to a voltage (V.sub.P, V.sub.N) of lower magnitude than the input signal to limit the voltage applied to the gate of the protected transistor to a value within the stress voltage of the protected transistor.

Abstract: An SRAM memory cell (40) uses GCMOS transistors (42, 44, 56, and 58) for improving discharge of complementary bit lines (60 and 62). The GCMOS transistors (42, 44, 56, and 58) have a graded-channel region on only the source side of the transistors. Configuring the pass-transistors (56 and 58) having the drain terminals connected to the complementary bit lines (60 and 62) and the cross-coupled transistors (42 and 44) having drain terminals connected to the memory cell outputs improves timing for a read operation of the memory cell (40).

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60, 97) that can be used to transport electrical signals across the device (10).

Abstract: An insulated gate semiconductor device (10) has a double spacer gate structure (45). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate oxide (23) is then formed over the major surface (12) adjacent the sidewalls (22). A first polysilicon layer (24) is deposited on the gate oxide (23) and the stack. The first polysilicon layer (24) is etched to form a first conductive spacer (32) of the gate structure (45). A second polysilicon layer (44) is deposited on first spacer (32) and the stack. The second polysilicon layer (44) is then etched to form a second conductive spacer (46) of the gate structure (45). Because the double spacer gate structure (45) is formed without relying on photolithographic techniques, its size is smaller than the size of a gate structure formed using conventional photolithography.

Abstract: A differential amplifier (10) includes three unilateral field effect transistors (12, 14, 16) formed in a common well (40) of a semiconductor material. Each of the three unilateral field effect transistors (12, 14, 16) has an asymmetric channel doping profile. The performance of the differential amplifier (10) is significantly improved by properly orienting the three unilateral field effect transistors (12, 14, 16).

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60,97) that can be used to transport electrical signals across the device (10).

Abstract: A compact diode-connected semiconductor device (20) and a method of manufacturing the field effect transistor (10). A doped layer (44) is formed in a semiconductor substrate (41) which serves as a drain extension region. An oxide layer (46) is formed on the semiconductor substrate (41) and an opening (50) is formed in the oxide layer (46). A gate structure (81) having an active gate portion (78) and a gate shorting structure (22) are formed on the oxide layer (46). The gate shorting structure (22) and the portion of the semiconductor substrate (41) adjacent the active gate portion (78) are doped with an impurity material of the same conductivity type as the doped layer (44). The gate shorting structure (22) serves as a source of impurity material for the drain region.

Abstract: A graded-channel semiconductor device (10) includes a substrate region (11) having a major surface (12). A source region (13) and a drain region (14) are formed in the substrate region (11) and are spaced apart to form a channel region (16). A doped region (18) is formed in the channel region (16) and is spaced apart from the source region (13), the drain region (14), and the major surface (12). The doped region (18) has the same conductivity type as the channel region (16), but has a higher dopant concentration. The device (10) exhibits an enhanced punch-through resistance and improved performance compared to prior art short channel structures.

Abstract: An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor substrate (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).

Abstract: A non-volatile RAM circuit (10) uses ferro-electric capacitors (14, 16) to store data in a dormant state. Data is initially stored on the ferro-electric capacitors. The data stored on the ferro-electric capacitors is transferred to a memory cell (25) when the RAM circuit is powered up. Subsequent read operations after the power-up sequence obtain data from the memory cell instead of the ferro-electric capacitors. Any write operation during the power-up sequence is stored in the memory cell. When power is removed, the ferro-electric capacitors are updated with the present state of the memory cell. The endurance and data retention time of the ferro-electic capacitors increases by accessing data from the memory cell.