Abstract: The disclosure provides a handheld power tool, which at least includes a housing assembly, a handle assembly and a switch assembly. The switch assembly includes a button assembly and a push-pull assembly. When the push-pull assembly is configured to complete at least two actions, the button assembly is unlocked, the first action is to slide back and forth along the handle assembly, and the second action is to slide back and forth obliquely along the handle assembly. With the handheld power tool of the disclosure, a trigger switch can be unlocked by a palm, so as to improve a problem of poor comfort during use caused by unlocking the trigger switch by a thumb.

Abstract: In an embodiment, a digital output driver circuit comprises an output stage having first and second transistors. A drive stage is configured to drive control terminals of the first and second transistors and comprising switching circuitry and current generator circuitry. In a first configuration, the driver circuit is configured to connect a control terminal of the second transistor to the reference node to turn off the second transistor; and connect a first capacitance to the current generator circuitry and to a control terminal of the first transistor to turn on the first transistor. In a second configuration, the driver circuit is configured to turn off the first transistor and connect the control terminal of the second transistor to the current generator circuitry and to the second capacitance to turn on the second transistor.

Abstract: A method for dividing a graphical simulation model up into a first sub-model and a second sub-model includes: identifying at least one first block as belonging to the first sub-model and identifying at least one second block as belonging to the second sub-model based on a sampling time and/or a resource allocation; searching for cyclic groups of blocks, wherein a cyclic group whose blocks all have the same sampling time is deemed to be atomic; identifying non-cyclic groups of blocks; allocating individual blocks from the cyclic groups of blocks and the non-cyclic group of blocks to either the first sub-model or the second sub-model, wherein all blocks of an atomic cyclic group are allocated to the same sub-model; generating program code for the processor from the first sub-model; and generating a configuration bitstream for the programmable logic module from the second sub-model.

Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.

Abstract: In an embodiment, a digital output driver circuit comprises an output stage having first and second transistors. A drive stage is configured to drive control terminals of the first and second transistors and comprising switching circuitry and current generator circuitry. In a first configuration, the driver circuit is configured to connect a control terminal of the second transistor to the reference node to turn off the second transistor; and connect a first capacitance to the current generator circuitry and to a control terminal of the first transistor to turn on the first transistor. In a second configuration, the driver circuit is configured to turn off the first transistor and connect the control terminal of the second transistor to the current generator circuitry and to the second capacitance to turn on the second transistor.

Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.

Abstract: In an embodiment, a digital output driver circuit comprises an output stage having first and second transistors. A drive stage is configured to drive control terminals of the first and second transistors and comprising switching circuitry and current generator circuitry. In a first configuration, the driver circuit is configured to connect a control terminal of the second transistor to the reference node to turn off the second transistor; and connect a first capacitance to the current generator circuitry and to a control terminal of the first transistor to turn on the first transistor. In a second configuration, the driver circuit is configured to turn off the first transistor and connect the control terminal of the second transistor to the current generator circuitry and to the second capacitance to turn on the second transistor.

Abstract: In an embodiment, a digital output driver circuit comprises an output stage having first and second transistors. A drive stage is configured to drive control terminals of the first and second transistors and comprising switching circuitry and current generator circuitry. In a first configuration, the driver circuit is configured to connect a control terminal of the second transistor to the reference node to turn off the second transistor; and connect a first capacitance to the current generator circuitry and to a control terminal of the first transistor to turn on the first transistor. In a second configuration, the driver circuit is configured to turn off the first transistor and connect the control terminal of the second transistor to the current generator circuitry and to the second capacitance to turn on the second transistor.

Abstract: An electronic device includes a rectifier bridge that includes an input configured to be coupled to power over Ethernet (PoE) power sourcing equipment (PSE), and an output. A transistor is configured to selectively couple the output with a load. The electronic device includes a maintain power signature (MPS) device, and a control circuit. The control circuit is to maintain the transistor on when a load current is above a threshold, source current from the rectifier bridge to the MPS device when the load current is below the threshold, and switch the transistor to a diode configuration when the load current is below the threshold.

Abstract: An electronic device includes a rectifier bridge that includes an input configured to be coupled to power over Ethernet (PoE) power sourcing equipment (PSE), and an output. A transistor is configured to selectively couple the output with a load. The electronic device includes a maintain power signature (MPS) device, and a control circuit. The control circuit is to maintain the transistor on when a load current is above a threshold, source current from the rectifier bridge to the MPS device when the load current is below the threshold, and switch the transistor to a diode configuration when the load current is below the threshold.

Abstract: An electronic device includes a rectifier bridge that includes an input configured to be coupled to power over Ethernet (PoE) power sourcing equipment (PSE), and an output. A transistor is configured to selectively couple the output with a load. The electronic device includes a maintain power signature (MPS) device, and a control circuit. The control circuit is to maintain the transistor on when a load current is above a threshold, source current from the rectifier bridge to the MPS device when the load current is below the threshold, and switch the transistor to a diode configuration when the load current is below the threshold.

Abstract: An electronic device includes a rectifier bridge that includes an input configured to be coupled to power over Ethernet (PoE) power sourcing equipment (PSE), and an output. A transistor is configured to selectively couple the output with a load. The electronic device includes a maintain power signature (MPS) device, and a control circuit. The control circuit is to maintain the transistor on when a load current is above a threshold, source current from the rectifier bridge to the MPS device when the load current is below the threshold, and switch the transistor to a diode configuration when the load current is below the threshold.