Patents by Inventor Andreas AGNE

Andreas AGNE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12265771
    Abstract: A method for dividing a graphical simulation model up into a first sub-model and a second sub-model includes: identifying at least one first block as belonging to the first sub-model and identifying at least one second block as belonging to the second sub-model based on a sampling time and/or a resource allocation; searching for cyclic groups of blocks, wherein a cyclic group whose blocks all have the same sampling time is deemed to be atomic; identifying non-cyclic groups of blocks; allocating individual blocks from the cyclic groups of blocks and the non-cyclic group of blocks to either the first sub-model or the second sub-model, wherein all blocks of an atomic cyclic group are allocated to the same sub-model; generating program code for the processor from the first sub-model; and generating a configuration bitstream for the programmable logic module from the second sub-model.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: April 1, 2025
    Assignee: DSPACE GMBH
    Inventors: Dominik Lubeley, Andreas Agne
  • Publication number: 20220309218
    Abstract: A method for dividing a graphical simulation model up into a first sub-model and a second sub-model includes: identifying at least one first block as belonging to the first sub-model and identifying at least one second block as belonging to the second sub-model based on a sampling time and/or a resource allocation; searching for cyclic groups of blocks, wherein a cyclic group whose blocks all have the same sampling time is deemed to be atomic; identifying non-cyclic groups of blocks; allocating individual blocks from the cyclic groups of blocks and the non-cyclic group of blocks to either the first sub-model or the second sub-model, wherein all blocks of an atomic cyclic group are allocated to the same sub-model; generating program code for the processor from the first sub-model; and generating a configuration bitstream for the programmable logic module from the second sub-model.
    Type: Application
    Filed: March 17, 2022
    Publication date: September 29, 2022
    Inventors: Dominik Lubeley, Andreas Agne
  • Patent number: 11442884
    Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: September 13, 2022
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Andreas Agne, Dominik Lubeley, Heiko Kalte, Marc Schlenger
  • Publication number: 20210303501
    Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 30, 2021
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Andreas AGNE, Dominik LUBELEY, Heiko KALTE, Marc SCHLENGER