Abstract: The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.

Abstract: A method and corresponding apparatus is provided for determining the location of a configuration server being connected to a totally symmetric network infrastructure that does not exhibit any symmetry breakers on network level. The configuration server reaches a decision to determine its network-wide unique configuration in order to be able to serve controllers. This decision depends on the plug position of the configuration server under consideration and the assumption of plugging rules governing a “good” network infrastructure. The controllers periodically send network packets that will be marked if they traverse specific connection elements in the network. The origin and the path of a network packet can be determined. The decision making is based on a majority function based on the packets received by the configuration server. If a decision cannot be made, then errors in the cabling structure can be detected.

Abstract: A method and corresponding apparatus is provided for determining the location of a configuration server being connected to a totally symmetric network infrastructure that does not exhibit any symmetry breakers on network level. The configuration server reaches a decision to determine its network-wide unique configuration in order to be able to serve controllers. This decision depends on the plug position of the configuration server under consideration and the assumption of plugging rules governing a “good” network infrastructure. The controllers periodically send network packets that will be marked if they traverse specific connection elements in the network. The origin and the path of a network packet can be determined. The decision making is based on a majority function based on the packets received by the configuration server. If a decision cannot be made, then errors in the cabling structure can be detected.

Abstract: The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.

Abstract: The present invention relates to boot code processing of a computer system, and in particular to a method and respective system for managing boot code of a computer system, wherein the system comprises at least a first and a redundant second boot memory portion, and wherein the system is booted from one of said portions, referred to as the active booting portion, the other boot portion being in a stand-by mode and being referred to as inactive boot portion.

Abstract: The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.

Abstract: A method, apparatus, and computer instructions for managing requests for data by processes in a data processing system. Requests for data from the processes in slave mode are tracked. Data received by a device driver is stored, wherein the data may originate from multiple masters. The data is sent to the processes, wherein the device driver is not required to handle requests for the processes in slave mode.

Abstract: A method, apparatus, and computer instructions for managing requests for data by processes in a data processing system. Requests for data from the processes in slave mode are tracked. Data received by a device driver is stored, wherein the data may originate from multiple masters. The data is sent to the processes, wherein the device driver is not required to handle requests for the processes in slave mode.

Abstract: The present invention relates to boot code processing of a computer system, and in particular to a method and respective system for managing boot code of a computer system, wherein the system comprises at least a first and a redundant second boot memory portion, and wherein the system is booted from one of said portions, referred to as the active booting portion, the other boot portion being in a stand-by mode and being referred to as inactive boot portion.

Abstract: A recovery process for embedded processors monitors other processes in the system. Each process may specify a recovery policy residing in nonvolatile electronic memory that preferably includes a recovery count, a recovery time, and a recovery action. If a process terminates unexpectedly, the recovery process determines whether the process had a corresponding recovery policy. If not, the recovery process does not recover the process. If the process has a corresponding recovery policy, the recovery process determines whether it can recover the process by examining the recovery count and recovery time specified in the recovery policy. If the process can be recovered, the recovery process performs the recovery action specified in the corresponding recovery policy. If the process cannot be recovered, the recovery process resets the system.

Abstract: The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors, and wherein the ECC-bits cannot be accessed directly for a read or write process. In order to improve ECC testing, an ECC verification is proposed.

Abstract: A method, apparatus, and computer instructions for managing requests for data by processes in a data processing system. Requests for data from the processes in slave mode are tracked. Data received by a device driver is stored, wherein the data may originate from multiple masters. The data is sent to the processes, wherein the device driver is not required to handle requests for the processes in slave mode.

Abstract: A recovery process for embedded processors monitors other processes in the system. Each process may specify a recovery policy residing in nonvolatile electronic memory that preferably includes a recovery count, a recovery time, and a recovery action. If a process terminates unexpectedly, the recovery process determines whether the process had a corresponding recovery policy. If not, the recovery process does not recover the process. If the process has a corresponding recovery policy, the recovery process determines whether it can recover the process by examining the recovery count and recovery time specified in the recovery policy. If the process can be recovered, the recovery process performs the recovery action specified in the corresponding recovery policy. If the process cannot be recovered, the recovery process resets the system.