Patents by Inventor Andreas Baenisch

Andreas Baenisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040111545
    Abstract: A plurality of digital-analog converters and analog-digital converters are connected in the data lines between the connection contacts and the memory cells of a memory device. The memory can be read, written to and actuated by analog data transfers instead of the previous digital signals. The same volume of data, for which a plurality of connection contact areas were normally required, can thus be read via just one connection contact. Addressing the memory cells requires no more than respective contact areas for the analog row address and the analog column address, which are converted into digital addresses using analog-digital converters.
    Type: Application
    Filed: October 24, 2003
    Publication date: June 10, 2004
    Inventors: Franz-Xaver Obergruss-Berger, Andreas Baenisch, Ellen Toll
  • Patent number: 6724667
    Abstract: A data memory for storing data, having a memory cell array (2), which comprises a large number of memory cells (3), each of which can be addressed by means of a memory cell select transistor (4) connected to a word line (9) and to a bit line (13) and which have a storage capacity for storing one data bit, the memory cell array (2) containing redundant memory cells (3′), which are provided in order to replace memory cells (3) which have been produced wrongly, by means of readdressing, and having read amplifiers (22), which are in each case provided for the signal amplification of a data bit read from an addressed memory cell (3) via an associated bit line (13) and are supplied with a buffered supply voltage, the redundant memory cells (3′) which have not been readdressed being connected to the associated bit lines (13′) and additionally buffering the supply voltage for the read amplifiers (22).
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: April 20, 2004
    Assignee: Infineon Technologies AG
    Inventors: Andreas Baenisch, Sabine Kling
  • Patent number: 6613616
    Abstract: A method for fabricating a field-effect transistor situated within an integrated semiconductor circuit. At least two gate regions each extending between a source region and a drain region and are disposed such that they lie one above the other in a thickness direction of a substrate, thereby reducing the space requirement of the hitherto customary larger field-effect transistors in integrated semiconductor circuits.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: September 2, 2003
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Angermann, Andreas Bänisch
  • Patent number: 6603170
    Abstract: An integrated semiconductor circuit is described and has a semiconductor memory configuration embedded in a semiconductor chip and an interface circuit. The interface circuit is set up for the connection and transfer of data and control signals between the semiconductor memory configuration and a circuit periphery surrounding the memory configuration. The interface circuit is configured as a standard interface for all types of integrated semiconductor circuits with an embedded semiconductor memory configuration for the largest bit width that can be realized in the semiconductor memory configuration. A switch configuration is provided which switches off bits of the standard interface that are unused for smaller bit widths.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: August 5, 2003
    Assignee: Infineon Technologies AG
    Inventors: Andreas Bänisch, Marco Troost
  • Patent number: 6583508
    Abstract: The present invention provides an integrated circuit with a plurality of active strip-shaped regions (S1, D1, S2, D2, S3) arranged in parallel next to one another; a contact level (K2) with a respective plurality of contacts (9′; 11, 12) arranged regularly in the longitudinal direction of the individual strip-shaped regions (S1, D1, S2, D2, S3); the contacts (9′; 11, 12) being arranged in the widthwise direction of the individual strip-shaped regions (S1, D1, S2, D2, S3) in such a way that the widthwise extent of corresponding contacts (9′; 11, 12) of neighboring regions varies.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: June 24, 2003
    Assignee: Infineon Technologies AG
    Inventors: Andreas Baenisch, Sabine Kling
  • Patent number: 6515374
    Abstract: An integrated semiconductor chip has at least two metal interconnects of two different metallization planes, which are disposed parallel to one another. The metal interconnects are connected to one another via at least one electrically conductive contact point. The metal interconnects, for each direction, run orthogonally with respect to one another in a first region. For each direction, they run parallel to one another and at an oblique angle to the directions of the metal interconnects of the first region in a second region (20), in which they are contact-connected to one another. This configuration makes it possible, with little influence of electromigration, to have a comparatively small space requirement needed for the contact connection of mutually orthogonal interconnects.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: February 4, 2003
    Assignee: Infineon Technologies AG
    Inventors: Andreas Bänisch, Sabine Kling
  • Publication number: 20020190278
    Abstract: The present invention provides an integrated circuit with a plurality of active strip-shaped regions (S1, D1, S2, D2, S3) arranged in parallel next to one another; a contact level (K2) with a respective plurality of contacts (9′; 11, 12) arranged regularly in the longitudinal direction of the individual strip-shaped regions (S1, D1, S2, D2, S3); the contacts (9′; 11, 12) being arranged in the widthwise direction of the individual strip-shaped regions (S1, D1, S2, D2, S3) in such a way that the widthwise extent of corresponding contacts (9′; 11, 12) of neighboring regions varies.
    Type: Application
    Filed: April 23, 2002
    Publication date: December 19, 2002
    Inventors: Andreas Baenisch, Sabine Kling
  • Publication number: 20020172083
    Abstract: A data memory for storing data, having a memory cell array (2), which comprises a large number of memory cells (3), each of which can be addressed by means of a memory cell select transistor (4) connected to a word line (9) and to a bit line (13) and which have a storage capacity for storing one data bit, the memory cell array (2) containing redundant memory cells (3′), which are provided in order to replace memory cells (3) which have been produced wrongly, by means of readdressing, and having read amplifiers (22), which are in each case provided for the signal amplification of a data bit read from an addressed memory cell (3) via an associated bit line (13) and are supplied with a buffered supply voltage, the redundant memory cells (3′) which have not been readdressed being connected to the associated bit lines (13′) and additionally buffering the supply voltage for the read amplifiers (22).
    Type: Application
    Filed: April 29, 2002
    Publication date: November 21, 2002
    Applicant: Infineon Technologies AG
    Inventors: Andreas Baenisch, Sabine Kling