Abstract: A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions. A printed circuit board having a multiplicity of DRAM memory elements mounted thereto is arranged in a data path having a width of 144 bits. The SIMM further includes on-board drivers to buffer and drive signals in close proximity to the memory elements. In addition, electrically conductive traces are routed on the circuit board to reduce loading and trace capacitance to minimize signal skew to the distributed memory elements. The SIMM further includes a high pin density dual read-out connector structure receiving electrical traces from both sides of the circuit board for enhanced functionality. The SIMM is installed in complementary sockets one SIMM at a time to provide memory expansion in full width increments.

Abstract: A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions is disclosed. A printed circuit board having a multiplicity of DRAM memory elements mounted thereto is arranged in a data path having a width of 144 bits. The SIMM of the present invention further includes on-board drivers to buffer and drive signals in close proximity to the memory elements. In addition, electrically conductive traces are routed on the circuit board in such a manner to reduce loading and trace capacitance to minimize signal skew to the distributed memory elements. The SIMM further includes a high pin density dual readout connector structure receiving electrical traces from both sides of the circuit board for enhanced functionality. The SIMM is installed in complementary sockets one SIMM, at a time to provide memory expansion in full width increments.

Abstract: A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions is disclosed. A printed circuit board having a multiplicity of DRAM memory elements mounted thereto is arranged in a data path having a width of 144 bits. The SIMM of the present invention further includes on-board drivers to buffer and drive signals in close proximity to the memory elements. In addition, electrically conductive traces are routed on the circuit board in such a manner to reduce loading and trace capacitance to minimize signal skew to the distributed memory elements. The SIMM further includes a high pin density dual readout connector structure receiving electrical traces from both sides of the circuit board for enhanced functionality. The SIMM is installed in complementary sockets one SIMM at a time to provide memory expansion in full width increments.

Abstract: A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions is disclosed. A printed circuit board having a multiplicity of DRAM memory elements mounted thereto is arranged in a data path having a width of 144 bits. The SIMM of the present invention further includes on-board drivers to buffer and drive signals in close proximity to the memory elements. In addition, electrically conductive traces are routed on the circuit board in such a manner to reduce loading and trace capacitance to minimize signal skew to the distributed memory elements. The SIMM further includes a high pin density dual read-out connector structure receiving electrical traces from both sides of the circuit board for enhanced functionality. The SIMM is installed in complementary sockets one SIMM at a time to provide memory expansion in full width increments.

Abstract: A multiple bus architecture for flexible communication between processors, memory subsystems, and specialized subsystems over multiple high performance communication pathways. The multiple bus architecture enables flexible communication between processors and devices coupled to a multiprocessor bus, a system interconnect bus, an external bus, an input/output bus, and a memory subsystem. Processor modules coupled to multiprocessor bus slots access the memory subsystem over the multiprocessor bus. System interconnect modules coupled to system interconnect bus slots access the memory subsystem via the system interconnect bus, and the multiprocessor bus. Processor modules coupled to multiprocessor bus slots access devices on the external bus via the system interconnect bus.

Abstract: An improved high speed data transfer bus with virtual memory capability is disclosed. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. Moreover, the present invention minimizes the number of lines required to implement the bus. The present invention also minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Moreover, the present invention employs control signals that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.

Abstract: An improved high speed data transfer bus with virtual memory capability is disclosed. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. Moreover, the present invention minimizes the number of lines required to implement the bus. The present invention also minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Moreover, the present invention employs control signals that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.

Abstract: A high speed data transfer bus with virtual memory capability. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. This minimizes the number of lines required to implement the bus and minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Control signals are employed that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.

Abstract: The present invention provides an improved arbitrator for use in allocating access to a common resource coupled to a plurality of data processing devices ("agents"). An arbitrator is coupled between the resource and each of the agents, for selectively enabling individual agents to access the resource in accordance with a predetermined priority hierarchy. The arbitrator, in the presently preferred embodiment, receives request signals transmitted by an agent desiring to access the resource and allocates ownership on a first come first serve basis or by a four level hierarchy in the case of simultaneous requests. The arbitrator includes a timing circuit which times predetermined periods between request signals transmitted by the agent which has acquired ownership. The arbitrator senses multiple requests for access by the agent within the predetermined time period, and, enters a lock condition if the agent issues a second request within the predefined period.

Abstract: A computer memory architecture is most advantageously used in conjunction with a digital computer, to provide an improved high speed graphics display capability. Data representative of digital images to be displayed is generated and/or manipulated by a display processor and stored within a selected portion of the display processor's main memory. Subsequent modifications to the stored image are effectuated by the display processor reading the data from its main memory, performing appropriate operations on the data, and writing the data back into the main memory. Updated images are transferred to an buffer memory which sequentially stores the images in the order in which they were updated by the display processor. Data representative of an updated image is then transferred to the display frame buffer of the particular display system for subsequent display. Data is transferred from the buffer memory to the frame buffer during periods when the frame buffer is not refreshing the display.

Abstract: An improved memory management system is described having particular application for use in computer systems employing virtual memory techniques. The system includes a CPU and other data processing devices, such as I/O devices, direct memory access (DMA) units, a system bus, etc., which are coupled to a "virtual" address bus for transferring virtual address information to a main memory unit (MMU). Access to the virtual bus is controlled by arbitration unit in order to insure that only a single device may communicate with the MMU at a time. In a preferred embodiment, address space within the MMU is allocated into a plurality of memory spaces, each space including translation data for use by a particular data processing device coupled to the virtual bus. A device gaining access to the virtual bus identifies the particular MMU memory space to be used for its address translation by providing unique context bits denoting the memory space to the MMU.

Abstract: An apparatus for manipulating and displaying raster images stored in a memory system under computer control, wherein a function unit combines new display data presented to the apparatus with display data already stored in memory, to form a new display that is stored in memory system, all in a single read/modify/write cycle.