Patents by Inventor Andreas Behrendt

Andreas Behrendt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240091118
    Abstract: Cosmetic water-in-oil emulsion (W/O emulsion) containing a) polyglyceryl-4 diisostearate/polyhydroxystearate/sebacate and b) hydrogenated castor oil (INCI: Hydrogenated Castor Oil), wherein the preparation is free from mineral oil, paraffin wax, microcrystalline wax, shellac wax and polyethylene wax, free from polyacrylates, acrylate/C10-C30 alkyl acrylate crosspolymers and vinylpyrrolidone/hexadecene copolymers, and free from 3-(4-methylbenzylidene)camphor, 2-hydroxy-4-methoxybenzophenone (INCI: Oxybenzone), 2-ethylhexyl 4-methoxycinnamate (INCI Octyl Methoxycinnamate), ethylhexyl 2-cyano-3,3-diphenylacrylate (INCI: Octocrylene), parabens (particularly methyl, propyl and butyl paraben), methylisothiazolinone, chloromethylisothiazolinone and DMDM hydantoin, polyethylene glycol ethers or polyethylene glycol esters.
    Type: Application
    Filed: January 13, 2022
    Publication date: March 21, 2024
    Inventors: Katharina HERWIG, Andreas BLECKMANN, Petra KOCH, Katharina ROPETER, Theresa BEHRENDT, Keti SCHUERINGS
  • Patent number: 11804432
    Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a metal structure above the first main surface. The metal structure has a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material contacts and covers at least the periphery region of the metal structure. A thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section. An average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: October 31, 2023
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Sergey Ananiev, Andreas Behrendt, Holger Doepke, Uwe Schmalzbauer, Michael Sorger, Dominic Thurmer
  • Patent number: 11621520
    Abstract: An electrical data connector includes a socket having a socket body that defines a plug connector cavity and electrically conductive shields within the cavity. A plug connector has a plug body telescopically slid into the plug connector cavity. The plug body has an insert cavity and adjacent spring openings, each of the spring openings aligning with a respective one of the shields. A cable head has an insert module telescopically slid into the insert cavity. The cable head includes an electrically conductive fixation element that is fixed to the insert module and fixed to a cable. The fixation element includes integral spring elements that extend generally radially outwardly from the insert module and are each configured to extend through respective spring openings into contact with respective shields.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: April 4, 2023
    Assignee: Lear Corporation
    Inventors: Yasin Canol, Andreas Behrendt, Marlon Christian Grosser
  • Publication number: 20230082571
    Abstract: A power semiconductor device includes a semiconductor body and a first terminal at the semiconductor body. The first terminal has a first side for adjoining an encapsulation and a second side for adjoining the semiconductor body. The first terminal includes, at the first side, a top layer; and, at the second side, a base layer coupled with the top layer, wherein a sidewall of the top layer and/or a sidewall of the base layer is arranged in an angle smaller than 85° with respect to a plane.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 16, 2023
    Inventors: Jochen HILSENBECK, Thomas SOELLRADL, Roman ROTH, Annette SAENGER, Ulrike FASTNER, Johanna SCHLAMINGER, Joachim HIRSCHLER, Andreas BEHRENDT
  • Patent number: 11501979
    Abstract: A semiconductor device and a method of producing the semiconductor device are described. The semiconductor device includes: a semiconductor substrate; a metallization layer over the semiconductor substrate; a plating over the metallization layer, the plating including NiP; a passivation over the metallization layer and laterally adjacent the plating such that a surface of the plating that faces away from the semiconductor substrate is uncovered by the passivation, wherein a seam is present along an interface between the passivation and the plating; and a structure that covers the seam along a periphery of the plating and delimits a bondable area for the plating. The structure extends from the periphery of the plating onto the passivation. The structure includes an imide having a curing temperature below a recrystallization temperature of the NiP or an oxide having a deposition temperature below the recrystallization temperature of the NiP.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: November 15, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Beninger-Bina, Andreas Behrendt, Mark Harrison, Robert Hartl, Peter Imrich, Reinhard Lindner, Evelyn Napetschnig
  • Publication number: 20220285149
    Abstract: Described herein are a method and a power semiconductor device produced by the method. The power semiconductor device includes: transistor device structures formed in a semiconductor substrate; a structured metallization layer above the semiconductor substrate; a first passivation over the structured metallization layer; a second passivation on the first passivation; an opening in the first passivation and the second passivation such that a first part of the structured metallization layer has a contact region uncovered by the first passivation and the second passivation and a peripheral region laterally surrounding the contact region and covered by the first passivation and the second passivation; a plating that covers the contact region but not the peripheral region of the first part of the structured metallization layer; and a protective layer separating the peripheral region of the first part of the structured metallization layer from the first passivation.
    Type: Application
    Filed: May 26, 2022
    Publication date: September 8, 2022
    Inventors: Ravi Keshav Joshi, Andreas Behrendt, Richard Gaisberger, Anita Satz, Johanna Schlaminger, Johann Schmid, Mario Stanovnik, Juergen Steinbrenner
  • Publication number: 20220254713
    Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a metal structure above the first main surface. The metal structure has a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material contacts and covers at least the periphery region of the metal structure. A thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section. An average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.
    Type: Application
    Filed: February 11, 2021
    Publication date: August 11, 2022
    Inventors: Markus Zundel, Sergey Ananiev, Andreas Behrendt, Holger Doepke, Uwe Schmalzbauer, Michael Sorger, Dominic Thurmer
  • Patent number: 11387095
    Abstract: Described herein is a method and a power semiconductor device produced by the method. The method includes: forming a structured metallization layer above a semiconductor substrate; forming a protective layer on the structured metallization layer; forming a first passivation over the structured metallization layer with the protective layer interposed between the first passivation and the structured metallization layer; structuring the first passivation to expose one or more regions of the protective layer; removing the one or more exposed regions of the protective layer to expose one or more parts of the structured metallization layer; and after structuring the first passivation and removing the one or more exposed regions of the protective layer, forming a second passivation on the first passivation and electroless plating the one or more exposed parts of the structured metallization layer.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: July 12, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Ravi Keshav Joshi, Andreas Behrendt, Richard Gaisberger, Anita Satz, Johanna Schlaminger, Johann Schmid, Mario Stanovnik, Juergen Steinbrenner
  • Publication number: 20220190505
    Abstract: An electrical connector includes a housing that has a housing first end, a housing second end, and a housing main body that defines a recess, a recess base, a projection, a projection end, and a plurality of terminal passageways. The recess extends from the housing first end toward the housing second end and to the recess base. The projection extends from the recess base toward the housing first end and to the projection end. Each terminal passageway of the plurality of terminal passageways has an inner wall. The inner wall has an inner wall first end, an inner wall second end, and an inner wall length that extends from the inner wall first end to the inner wall second end. The inner wall tapers along a portion of the inner wall length.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 16, 2022
    Applicant: Lear Corporation
    Inventors: Andreas Behrendt, Marcin Szatko, Yasin Canol, Marlon Christian Grosser
  • Publication number: 20220190515
    Abstract: An electrical data connector includes a socket having a socket body that defines a plug connector cavity and electrically conductive shields within the cavity. A plug connector has a plug body telescopically slid into the plug connector cavity. The plug body has an insert cavity and adjacent spring openings, each of the spring openings aligning with a respective one of the shields. A cable head has an insert module telescopically slid into the insert cavity. The cable head includes an electrically conductive fixation element that is fixed to the insert module and fixed to a cable. The fixation element includes integral spring elements that extend generally radially outwardly from the insert module and are each configured to extend through respective spring openings into contact with respective shields.
    Type: Application
    Filed: December 3, 2021
    Publication date: June 16, 2022
    Applicant: Lear Corporation
    Inventors: Yasin Canol, Andreas Behrendt, Marlon Christian Grosser
  • Publication number: 20220059347
    Abstract: Described herein is a method and a power semiconductor device produced by the method. The method includes: forming a structured metallization layer above a semiconductor substrate; forming a protective layer on the structured metallization layer; forming a first passivation over the structured metallization layer with the protective layer interposed between the first passivation and the structured metallization layer; structuring the first passivation to expose one or more regions of the protective layer; removing the one or more exposed regions of the protective layer to expose one or more parts of the structured metallization layer; and after structuring the first passivation and removing the one or more exposed regions of the protective layer, forming a second passivation on the first passivation and electroless plating the one or more exposed parts of the structured metallization layer.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 24, 2022
    Inventors: Ravi Keshav Joshi, Andreas Behrendt, Richard Gaisberger, Anita Satz, Johanna Schlaminger, Johann Schmid, Mario Stanovnik, Juergen Steinbrenner
  • Patent number: 9708182
    Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: July 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Behrendt, Kai-Alexander Schreiber, Sokratis Sgouridis, Martin Zgaga, Bernhard Winkler
  • Patent number: 9261791
    Abstract: Devices and methods are provided where photoresist is applied on a substrate and at least some regions of the photoresist are dried prior to removing a substrate from a substrate support.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Walter, Andreas Behrendt
  • Publication number: 20150368097
    Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.
    Type: Application
    Filed: August 28, 2015
    Publication date: December 24, 2015
    Inventors: Andreas Behrendt, Kai-Alexander Schreiber, Sokratis Sgouridis, Martin Zgaga, Bernhard Winkler
  • Patent number: 9142444
    Abstract: A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: September 22, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Markus Zundel, Erwin Bacher, Andreas Behrendt, Joerg Ortner, Walter Rieger, Rudolf Zelsacher
  • Patent number: 9139427
    Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: September 22, 2015
    Assignee: Infineon Technologies AG
    Inventors: Andreas Behrendt, Kai-Alexander Schreiber, Sokratis Sgouridis, Martin Zgaga, Bernhard Winkler
  • Publication number: 20150262814
    Abstract: A power semiconductor device in accordance with various embodiments may include: a semiconductor body; and a passivation layer disposed over at least a portion of the semiconductor body, wherein the passivation layer includes an organic dielectric material having a water uptake of less than or equal to 0.5 wt % in saturation.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 17, 2015
    Applicant: Infineon Technologies AG
    Inventors: Mathias Plappert, Eric Graetz, Andreas Behrendt, Oliver Humbel, Carsten Schaeffer, Angelika Koprowski
  • Publication number: 20140272705
    Abstract: Devices and methods are provided where photoresist is applied on a substrate and at least some regions of the photoresist are dried prior to removing a substrate from a substrate support.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Walter, Andreas Behrendt
  • Publication number: 20130323905
    Abstract: A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench.
    Type: Application
    Filed: May 15, 2013
    Publication date: December 5, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Markus ZUNDEL, Erwin BACHER, Andreas BEHRENDT, Joerg ORTNER, Walter RIEGER, Rudolf ZELSACHER
  • Publication number: 20130270658
    Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.
    Type: Application
    Filed: April 17, 2013
    Publication date: October 17, 2013
    Applicant: Infineon Technologies AG
    Inventors: Andreas Behrendt, Kai-Alexander Schreiber, Sokratis Sgouridis, Martin Zgaga, Bernhard Winkler