Patents by Inventor Andreas Burg
Andreas Burg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12068027Abstract: A fin field-effect transistor (FinFET) based semiconductor memory array having a plurality of memory cells, each memory cell including a write transistor having a write wordline gate over a first fin connected to a write wordline gate contact, a write bitline contact in connection with the first fin, and a storage node contact in connection with the first fin, and a read transistor having a storage node gate over a second fin, the storage node gate connected to a storage node gate contact, the storage node gate contact connected to the storage node contact, a read wordline contact in connection with the second fin, and a read bitline contact in connection with the second fin, wherein the write wordline gate and the storage node gate are arranged in series to each other along an extension axis that coincides with an longitudinal axis of the write wordline gate and a longitudinal axis of the storage node gate.Type: GrantFiled: August 18, 2022Date of Patent: August 20, 2024Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: Robert Giterman, Andreas Burg, Halil Andac Yigit
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Patent number: 12057858Abstract: A method of accessing a memory space of a memory device with a decoder, the memory space having faults, including the steps of performing a memory access operation by an electronic device to a access a logical memory space of the memory device, and randomizing the memory access operation with a randomization logic to access data from a physical memory space based on the logical memory space, the randomization logic providing time varying behavior for accessing the physical memory space.Type: GrantFiled: September 23, 2021Date of Patent: August 6, 2024Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: Andreas Burg, Reza Ghanaatian
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Publication number: 20240062811Abstract: A fin field-effect transistor (FinFET) based semiconductor memory array having a plurality of memory cells, each memory cell including a write transistor having a write wordline gate over a first fin connected to a write wordline gate contact, a write bitline contact in connection with the first fin, and a storage node contact in connection with the first fin, and a read transistor having a storage node gate over a second fin, the storage node gate connected to a storage node gate contact, the storage node gate contact connected to the storage node contact, a read wordline contact in connection with the second fin, and a read bitline contact in connection with the second fin, wherein the write wordline gate and the storage node gate are arranged in series to each other along an extension axis that coincides with an longitudinal axis of the write wordline gate and a longitudinal axis of the storage node gate.Type: ApplicationFiled: August 18, 2022Publication date: February 22, 2024Inventors: Robert Giterman, Andreas Burg, Halil Andac Yigit
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Publication number: 20220122686Abstract: A method of accessing a memory space of a memory device with a decoder, the memory space having faults, including the steps of performing a memory access operation by an electronic device to a access a logical memory space of the memory device, and randomizing the memory access operation with a randomization logic to access data from a physical memory space based on the logical memory space, the randomization logic providing time varying behavior for accessing the physical memory space.Type: ApplicationFiled: September 23, 2021Publication date: April 21, 2022Inventors: Andreas Burg, Reza Ghanaatian
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Patent number: 10002660Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.Type: GrantFiled: June 26, 2017Date of Patent: June 19, 2018Assignee: Bar-Ilan UniversityInventors: Robert Giterman, Adam Teman, Pascal Meinerzhagen, Andreas Burg, Alexander Fish
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Publication number: 20170294221Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Inventors: Robert GITERMAN, Adam Teman, Pascal Meinerzhagen, Andreas Burg, Alexander Fish
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Patent number: 9760536Abstract: A method and device for reducing the computational complexity of a processing algorithm, of a discrete signal, in particular of the spectral estimation and analysis of bio-signals, with minimum or no quality loss, which comprises steps of (a) choosing a domain, such that transforming the signal to the chosen domain results to an approximately sparse representation, wherein at least part of the output data vector has zero or low magnitude elements; (b) converting the original signal in the domain chosen in step (a) through a mathematical transform consisting of arithmetic operations resulting in a vector of output data; (c) reformulating the processing algorithm of the original signal in the original domain into a modified algorithm consisting of equivalent arithmetic operations in the domain chosen in step (a) to yield the expected result with the expected quality quantified in terms of a suitable application metric; (d) combining the mathematical transform of step (b) and the equivalent mathematical operatioType: GrantFiled: August 15, 2013Date of Patent: September 12, 2017Assignee: Ecole Polytechnique Fédérale de Lausanne (EPFL)Inventors: Georgios Karakonstantis, Aviinaash Sankaranarayanan, Andreas Burg, Srinivasan Murali, David Atienza Alonso
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Patent number: 9691445Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.Type: GrantFiled: April 30, 2015Date of Patent: June 27, 2017Assignee: Bar-Ilan UniversityInventors: Robert Giterman, Adam Teman, Pascal Meinerzhagen, Andreas Burg, Alexander Fish
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Publication number: 20170062024Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.Type: ApplicationFiled: April 30, 2015Publication date: March 2, 2017Inventors: Robert GITERMAN, Adam TEMAN, Pascal MEINERZHAGEN, Andreas BURG, Alexander FISH
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Publication number: 20150220486Abstract: A method and device for reducing the computational complexity of a processing algorithm, of a discrete signal, in particular of the spectral estimation and analysis of bio-signals, with minimum or no quality loss, which comprises steps of (a) choosing a domain, such that transforming the signal to the chosen domain results to an approximately sparse representation, wherein at least part of the output data vector has zero or low magnitude elements; (b) converting the original signal in the domain chosen in step (a) through a mathematical transform consisting of arithmetic operations resulting in a vector of output data; (c) reformulating the processing algorithm of the original signal in the original domain into a modified algorithm consisting of equivalent arithmetic operations in the domain chosen in step (a) to yield the expected result with the expected quality quantified in terms of a suitable application metric; (d) combining the mathematical transform of step (b) and the equivalent mathematical operatioType: ApplicationFiled: August 15, 2013Publication date: August 6, 2015Inventors: Georgios Karakonstantis, Aviinaash Sankaranarayanan, Andreas Burg, Srinivasan Murali, David Atienza Alonso
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Patent number: 7782971Abstract: The method for decoding a received signal in a multiple input/multiple output system uses QR-decomposition of the linear channel matrix, but then applies a non-Euclidean norm during tree traversal. Two separate hardware units, namely an MCU and a MEU, art provided for concurrent operation. The MCU determines a next child node, while the MEU determines next best parent nodes on the previously processed tree levels, which makes it possible to retrace the path to a next starting node without investing dedicated processing steps (e.g., cycles). On each tree level, the possible coordinates are grouped into several circular sets in the complex plane, and a series of decision boundaries is calculated for each set that allows a quick evaluation of the optimum coordinate in each set.Type: GrantFiled: September 14, 2005Date of Patent: August 24, 2010Assignee: ETH ZurichInventors: Andreas Burg, Moritz Borgmann, Markus Wenk, Martin Zellweger
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Patent number: 7742536Abstract: The present application describes a method for transmitting data through a MIMO-OFDM system which requires the computation of a function f(H(sk)), where H is the channel matrix and sk=exp(j*2*pi*k/N). The method splits function f into a first, nonpolynomial part, which is in turn a function of one or more polynomial functions in sk.Type: GrantFiled: November 7, 2005Date of Patent: June 22, 2010Assignee: Eth Zurich Eth TransferInventors: Andreas Burg, Helmut Bölcskei, Moritz Borgmann, Davide Cescato, Jan Hansen
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Publication number: 20090304114Abstract: The performance of multiple-input multiple-output (MIMO) systems, employing coding with multiple antennas depends heavily on the demapper algorithm which is used for MIMO detection. Soft-output demappers lead to better bit error rate (BER) performance compared to hard-decision demappers, but have a higher implementation complexity. The algorithm, proposed in this paper, relies on low-complexity harddecision MIMO detection. The reliability information for the received bits used to compute log-likelihood ratios is based on an estimate of the average bit error rate which is for example derived from the corresponding channel state information only. The algorithm is applicable to any hard-decision MIMO detector. As an example, we describe the application of the scheme to a linear MMSE detector and to sphere decoding with early termination.Type: ApplicationFiled: March 5, 2007Publication date: December 10, 2009Applicant: ETH ZÜRICHInventor: Andreas Burg
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Publication number: 20090063106Abstract: The method for decoding a received signal in a multiple input/multiple output system uses QR-decomposition of the linear channel matrix, but then applies a non-Euclidean norm during tree traversal. Two separate hardware units, namely an MCU and a MEU, art provided for concurrent operation. The MCU determines a next child node, while the MEU determines next best parent nodes on the previously processed tree levels, which makes it possible to retrace the path to a next starting node without investing dedicated processing steps (e.g., cycles). On each tree level, the possible coordinates are grouped into several circular sets in the complex plane, and a series of decision boundaries is calculated for each set that allows a quick evaluation of the optimum coordinate in each set.Type: ApplicationFiled: September 14, 2005Publication date: March 5, 2009Applicant: ETH ZURICHInventors: Andreas Burg, Moritz Borgmann, Markus Wenk, Martin Zellweger
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Publication number: 20080317141Abstract: The present application describes a method for transmitting data through a MIMO-OFDM system which requires the computation of a function f(H(sk)), where H is the channel matrix and sk=exp(j*2*pi*k/N). The method splits function f into a first, nonpolynomial part, which is in turn a function of one or more polynomial functions in sk.Type: ApplicationFiled: November 7, 2005Publication date: December 25, 2008Inventors: Andreas Burg, Helmut Bolcskei, Moritz Borgmann, Davide Cescato, Jan Hansen
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Patent number: 5593217Abstract: An information lamp flashes when instability is detected, whether the system is switched on, off or limited in its functional scope. When the traction control system is switched off or limited in its functional scope and no instability is detected, the lamp lights up continuously.Type: GrantFiled: September 19, 1995Date of Patent: January 14, 1997Assignee: Robert Bosch GmbHInventors: Johannes Schmitt, Andreas Burg, Ralf Donath
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Patent number: 5544949Abstract: When a first drive wheel is braked as a function of slippage at that wheel, braking intervention at the second drive wheel is precluded until the braking intervention at the first drive wheel is essentially terminated. This produces a locking differential effect.Type: GrantFiled: September 19, 1995Date of Patent: August 13, 1996Assignee: Robert Bosch GmbHInventors: Johannes Schmitt, Andreas Burg, Ralf Donath
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Patent number: 5544950Abstract: The slip of at least one driven wheel is compared to a predetermined threshold and the wheel is braked or torque is reduced when the threshold is exceeded. The slip threshold is raised when an impermissible difference between diameters of the tires on driven wheels is detected.Type: GrantFiled: December 30, 1994Date of Patent: August 13, 1996Assignee: Robert Bosch GmbHInventors: Andreas Burg, Johannes Schmitt
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Patent number: 5419622Abstract: Described is a drive-slip control system in which increase and reduction in pressure are produced by series of pulses. The pulse lengths are selected such that each pulse produces the same change in pressure. The difference between pressure-increase and pressure-reduction pulses is then a measure of the pressure at the wheel brake and can, for instance, be taken into account in an additionally fitted engine-torque governor.Type: GrantFiled: January 12, 1994Date of Patent: May 30, 1995Assignee: Robert Bosch GmbHInventors: Andreas Burg, Thomas Isella, Johannes Schmitt