Abstract: Embodiments of the invention provide a computer-implemented method for updating firmware of a Universal Serial Bus (USB) device. The USB device is configured to execute one or more applications of the USB device in a normal mode of operation of the USB device. The USB device includes a device descriptor indicative of one or more configuration descriptors, wherein a configuration descriptor is indicative of endpoints for data and command exchange. The device descriptor can be modified by adding a predefined bootloader configuration descriptor to the configurations descriptors for updating the firmware.

Abstract: Embodiments of the invention provide a computer-implemented method for updating firmware of a Universal Serial Bus (USB) device. The USB device is configured to execute one or more applications of the USB device in a normal mode of operation of the USB device. The USB device includes a device descriptor indicative of one or more configuration descriptors, wherein a configuration descriptor is indicative of endpoints for data and command exchange. The device descriptor can be modified by adding a predefined bootloader configuration descriptor to the configurations descriptors for updating the firmware.

Abstract: A checkpointing module, a method for storing checkpoints and a microserver including a checkpointing module for storing checkpoints are proposed. The checkpointing module includes an interconnect interface configured to receive checkpoints from at least one compute module, one or more non-volatile random access memory devices configured to store the received checkpoints, a memory management entity configured to assign storage locations for the received checkpoints in the one or more non-volatile random access memory devices, and a memory controller configured to store the received checkpoints at the assigned storage locations.

Abstract: Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.

Abstract: Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.

Abstract: A buck converter for converting an input voltage into an output voltage including a first switch and a low-pass filter circuit comprising an inductor, a low-pass filter switching device and an output capacitor system. The output capacitor system comprises a parallel arrangement of a first path comprising a first capacitor and at least a second path comprising a serial connection of a second capacitor and a second switch. A controller is provided to turn on the first switch during an on-cycle, thereby switching the input voltage to the low-pass filter circuit, and to turn off the first switch during an off-cycle. The controller further turns off the second switch under normal load operations so that the second capacitor is not charged and turns on the second switch in case of a load reduction during the off-cycle so that the second capacitor is added to the output capacitor system by the second switch.

Abstract: A buck converter for converting an input voltage into an output voltage including a first switch and a low-pass filter circuit comprising an inductor, a low-pass filter switching device and an output capacitor system. The output capacitor system comprises a parallel arrangement of a first path comprising a first capacitor and at least a second path comprising a serial connection of a second capacitor and a second switch. A controller is provided to turn on the first switch during an on-cycle, thereby switching the input voltage to the low-pass filter circuit, and to turn off the first switch during an off-cycle. The controller further turns off the second switch under normal load operations so that the second capacitor is not charged and turns on the second switch in case of a load reduction during the off-cycle so that the second capacitor is added to the output capacitor system by the second switch.

Abstract: A checkpointing module, a method for storing checkpoints and a microserver including a checkpointing module for storing checkpoints are proposed. The checkpointing module includes an interconnect interface configured to receive checkpoints from at least one compute module, one or more non-volatile random access memory devices configured to store the received checkpoints, a memory management entity configured to assign storage locations for the received checkpoints in the one or more non-volatile random access memory devices, and a memory controller configured to store the received checkpoints at the assigned storage locations.

Abstract: A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect.

Abstract: A tunnel field-effect transistor including at least: a source region including a corresponding source semiconductor material; a drain region including a corresponding drain semiconductor material, and a channel region including a corresponding channel semiconductor material, which is arranged between the source region and the drain region. The tunnel field-effect transistor further includes at least: a source-channel gate electrode provided on an interface between the source region and the channel region; an insulator corresponding to the source-channel gate electrode that is provided between the source-channel gate electrode and the interface between the source region and the channel region; a drain-channel gate electrode provided on an interface between the drain region and the channel region; and an insulator corresponding to the drain-channel gate electrode that is provided between the drain-channel gate electrode and the interface between the drain region and the channel region.

Abstract: A method and system for balancing loads of a plurality of bus lanes of a snooping-based bus. The system includes: a receiver for receiving snoop transactions from the bus lanes, each of the snoop transactions having a snoop request and at least one snoop response, an analyzer for analyzing respective actual and expected loads of each of the bus lanes dependent on the received snoop transactions, and a controller for providing a next snoop request from a number of outstanding snoop requests to a buffer allocated to the system, where the buffer is dependent on the analyzed loads of the bus lanes.

Abstract: A computer system having a main unit and an expansion unit connected by an interface arrangement. The expansion unit includes at least one connector for receiving an input/output component, so that additional input/output components can be added to the computer system. The interface arrangement includes at least one cache controller and at least one cache memory for monitoring and predicting requests exchanged between the main unit and the expansion unit. A method of caching and processing input/output requests and a storage medium is also provided.

Abstract: The present invention provides a method and system for providing multi-level memory protection. The method includes defining a hierarchy of one or more parent process and their respective child processes. The method further includes building a data structure for defining access rights of each of the parent process and their respective child processes in the defined hierarchy.

Abstract: A tunnel field-effect transistor including at least: a source region including a corresponding source semiconductor material; a drain region including a corresponding drain semiconductor material, and a channel region including a corresponding channel semiconductor material, which is arranged between the source region and the drain region. The tunnel field-effect transistor further includes at least: a source-channel gate electrode provided on an interface between the source region and the channel region; an insulator corresponding to the source-channel gate electrode that is provided between the source-channel gate electrode and the interface between the source region and the channel region; a drain-channel gate electrode provided on an interface between the drain region and the channel region; and an insulator corresponding to the drain-channel gate electrode that is provided between the drain-channel gate electrode and the interface between the drain region and the channel region.

Abstract: A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect.

Abstract: A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect.

Abstract: A method and system for balancing loads of a plurality of bus lanes of a snooping-based bus. The system includes: a receiver for receiving snoop transactions from the bus lanes, each of the snoop transactions having a snoop request and at least one snoop response, an analyzer for analyzing respective actual and expected loads of each of the bus lanes dependent on the received snoop transactions, and a controller for providing a next snoop request from a number of outstanding snoop requests to a buffer allocated to the system, where the buffer is dependent on the analyzed loads of the bus lanes.

Abstract: A method for monitoring data congestion in a computer network with multiple nodes and for controlling data transmission in the computer network. The method includes generating a congestion notification by the node which detects a data congestion and transmitting the congestion notification to the data source which is involved in the data congestion. The method also includes generating in the data source a congestion value which indicates how severe the data congestion is, and storing in a worst case array of the data source those congestion values which indicate the most severe data congestions.

Abstract: A computer system controls ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered read responses. The system includes a memory and/or cache memory including a memory/cache controller, an I/O device for communicating memory access requests from system data sources and a memory controller I/O Interface. Memory access requests from the system data sources provide a respective ordering class value. The memory controller I/O Interface processes each memory access request and ordering class value communicated from a data source through the I/O device in coordination with the ordering class protocol. Preferably, the I/O device includes at least one register for storing ordering class values associated with system data sources that implement memory access requests.