Patents by Inventor Andreas D. Olofsson
Andreas D. Olofsson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8732440Abstract: A method for generating a digital signal pattern at M outputs involves retrieving an instruction from memory comprising a first set of bits identifying a first group of N outputs that includes fewer than all of the M outputs, and a second set of N bits each corresponding to a respective output included in the identified first group of N outputs. For each of the M outputs that is included in the identified first group of N outputs, the signal at the output is toggled if the one of the N bits corresponding to that output is in a first state and is kept in the same state if the one of the N bits corresponding to that output is in a second state. For each of the M outputs that is not included in the identified first group of N outputs, the signal at that output is kept in the same state.Type: GrantFiled: December 3, 2007Date of Patent: May 20, 2014Assignee: Analog Devices, Inc.Inventors: Christopher Jacobs, Andreas D. Olofsson, Paul Kettle
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Publication number: 20140074901Abstract: Multiplication engines and multiplication methods are provided for a digital processor.Type: ApplicationFiled: October 16, 2013Publication date: March 13, 2014Applicant: ANALOG DEVICES TECHNOLOGYInventors: Andreas D. Olofsson, Baruch Yanovitch
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Patent number: 8589469Abstract: Multiplication engines and multiplication methods are provided for a digital processor.Type: GrantFiled: January 10, 2008Date of Patent: November 19, 2013Assignee: Analog Devices TechnologyInventors: Andreas D. Olofsson, Baruch Yanovitch
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Patent number: 8275822Abstract: Multiplication engines and multiplication methods are provided. A multiplication engine for a digital processor includes a first multiplier to generate unequally weighted partial products from input operands in a first multiplier mode; a second multiplier to generate equally weighted partial products from input operands in a second multiplier mode; a multiplexer to select the unequally weighted partial products in the first multiplier mode and to select the equally weighted partial products in the second multiplier mode; and a carry save adder array configured to combine the selected partial products in the first multiplier mode and in the second multiplier mode.Type: GrantFiled: January 10, 2008Date of Patent: September 25, 2012Assignee: Analog Devices, Inc.Inventors: Andreas D. Olofsson, Baruch Yanovitch
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Patent number: 8135975Abstract: A first output count is compared with first and second stored count values for generating an output event at a first node if the first Output count corresponds to the first or second stored count values.Type: GrantFiled: June 14, 2007Date of Patent: March 13, 2012Assignee: Analog Devices, Inc.Inventor: Andreas D. Olofsson
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Patent number: 8006114Abstract: An apparatus for generating a digital signal pattern may comprises a memory, a program sequencer, first and second circuits, and an event execution unit. The memory may have stored therein a plurality of instructions that, when executed, cause a digital signal pattern to be generated on a plurality of nodes. The program sequencer may be configured to control a sequence in which the plurality of instructions are retrieved from the memory and executed. The first circuit may sequentially step through a plurality of different output states in response to a clock signal. The second circuit may identify an output event when an output state of the first circuit corresponds to an output state identified by retrieved instructions of a particular type. The event execution unit may control states of signals on the plurality of nodes in a manner specified by the retrieved instructions of the particular type in response to the second circuit identifying an output event.Type: GrantFiled: June 14, 2007Date of Patent: August 23, 2011Assignee: Analog Devices, Inc.Inventors: Andreas D. Olofsson, Christopher Jacobs, Paul Kettle
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Patent number: 7880492Abstract: An integrated circuit includes a substrate, a storage device formed in the substrate to hold bias settings, and operational blocks formed in the substrate, each operational block including an operational circuit and a charge pump to provide well bias voltages to the operational circuit in response to one or more of the bias settings. A method for testing an integrated circuit having two or more operational blocks includes: (a) determining a maximum operating speed of each of the blocks at a minimum supply voltage; (b) selecting a block that has a slow operating speed; (c) selecting a well bias to speed up the selected block; (d) selecting a supply voltage to meet a target operating frequency at the selected well bias and measuring power; (e) repeating acts (b)-(d) while the measured power is less than a baseline power; and (f) saving the selected well bias and supply voltage settings for operation of the integrated circuit.Type: GrantFiled: May 22, 2009Date of Patent: February 1, 2011Assignee: Analog Devices, Inc.Inventor: Andreas D. Olofsson
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Publication number: 20090231023Abstract: An integrated circuit includes a substrate, a storage device formed in the substrate to hold bias settings, and operational blocks formed in the substrate, each operational block including an operational circuit and a charge pump to provide well bias voltages to the operational circuit in response to one or more of the bias settings. A method for testing an integrated circuit having two or more operational blocks includes: (a) determining a maximum operating speed of each of the blocks at a minimum supply voltage; (b) selecting a block that has a slow operating speed; (c) selecting a well bias to speed up the selected block; (d) selecting a supply voltage to meet a target operating frequency at the selected well bias and measuring power; (e) repeating acts (b)-(d) while the measured power is less than a baseline power; and (f) saving the selected well bias and supply voltage settings for operation of the integrated circuit.Type: ApplicationFiled: May 22, 2009Publication date: September 17, 2009Applicant: Analog Devices, Inc.Inventor: Andreas D. Olofsson
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Patent number: 7538569Abstract: An integrated circuit includes a substrate, a storage device formed in the substrate to hold bias settings, and operational blocks formed in the substrate, each operational block including an operational circuit and a charge pump to provide well bias voltages to the operational circuit in response to one or more of the bias settings. A method for testing an integrated circuit having two or more operational blocks includes: (a) determining a maximum operating speed of each of the blocks at a minimum supply voltage; (b) selecting a block that has a slow operating speed; (c) selecting a well bias to speed up the selected block; (d) selecting a supply voltage to meet a target operating frequency at the selected well bias and measuring power; (e) repeating acts (b)-(d) while the measured power is less than a baseline power; and (f) saving the selected well bias and supply voltage settings for operation of the integrated circuit.Type: GrantFiled: October 2, 2007Date of Patent: May 26, 2009Assignee: Analog Devices, Inc.Inventor: Andreas D. Olofsson
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Publication number: 20090085578Abstract: An integrated circuit includes a substrate, a storage device formed in the substrate to hold bias settings, and operational blocks formed in the substrate, each operational block including an operational circuit and a charge pump to provide well bias voltages to the operational circuit in response to one or more of the bias settings. A method for testing an integrated circuit having two or more operational blocks includes: (a) determining a maximum operating speed of each of the blocks at a minimum supply voltage; (b) selecting a block that has a slow operating speed; (c) selecting a well bias to speed up the selected block; (d) selecting a supply voltage to meet a target operating frequency at the selected well bias and measuring power; (e) repeating acts (b)-(d) while the measured power is less than a baseline power; and (f) saving the selected well bias and supply voltage settings for operation of the integrated circuit.Type: ApplicationFiled: October 2, 2007Publication date: April 2, 2009Applicant: Analog Devices, Inc.Inventor: Andreas D. Olofsson
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Publication number: 20080219112Abstract: An apparatus for generating a digital signal pattern may comprises a memory, a program sequencer, first and second circuits, and an event execution unit. The memory may have stored therein a plurality of instructions that, when executed, cause a digital signal pattern to be generated on a plurality of nodes. The program sequencer may be configured to control a sequence in which the plurality of instructions are retrieved from the memory and executed. The first circuit may sequentially step through a plurality of different output states in response to a clock signal. The second circuit may identify an output event when an output state of the first circuit corresponds to an output state identified by retrieved instructions of a particular type. The event execution unit may control states of signals on the plurality of nodes in a manner specified by the retrieved instructions of the particular type in response to the second circuit identifying an output event.Type: ApplicationFiled: June 14, 2007Publication date: September 11, 2008Applicant: Analog Devices, Inc.Inventors: Andreas D. Olofsson, Christopher Jacobs, Paul Kettle
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Publication number: 20080222441Abstract: One disclosed circuit comprises a clock cycle counter circuit, a memory, and a clock cycle count comparison circuit. The clock cycle counter circuit may be configured to produce an output count. The memory may be configured to store at least first and second count values. The cycle count comparison circuit may be configured to compare the output count with each of the first and second stored count values and to generate a particular type of output event at a node if the output count corresponds to either of the first and second stored count values. Another disclosed circuit comprises a digital pattern generator, a general purpose output controller, at least one memory element, and a selection circuit. The digital pattern generator may be configured to generate a pattern of digital signals at M nodes. The general purpose output controller may be configured to generate general purpose digital signals at N nodes.Type: ApplicationFiled: June 14, 2007Publication date: September 11, 2008Applicant: Analog Devices, Inc.Inventor: Andreas D. Olofsson
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Publication number: 20080222226Abstract: Multiplication engines and multiplication methods are provided for a digital processor.Type: ApplicationFiled: January 10, 2008Publication date: September 11, 2008Applicant: Analog Devices, Inc.Inventors: Andreas D. Olofsson, Baruch Yanovitch
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Publication number: 20080222444Abstract: A method for generating a digital signal pattern at M outputs involves retrieving an instruction from memory comprising a first set of bits identifying a first group of N outputs that includes fewer than all of the M outputs, and a second set of N bits each corresponding to a respective output included in the identified first group of N outputs. For each of the M outputs that is included in the identified first group of N outputs, the signal at the output is toggled if the one of the N bits corresponding to that output is in a first state and is kept in the same state if the one of the N bits corresponding to that output is in a second state. For each of the M outputs that is not included in the identified first group of N outputs, the signal at that output is kept in the same state.Type: ApplicationFiled: December 3, 2007Publication date: September 11, 2008Applicant: Analog Devices, Inc.Inventors: Andreas D. Olofsson, Christopher Jacobs, Paul Kettle
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Publication number: 20080195685Abstract: Multiplication engines and multiplication methods are provided. A multiplication engine for a digital processor includes a first multiplier to generate unequally weighted partial products from input operands in a first multiplier mode; a second multiplier to generate equally weighted partial products from input operands in a second multiplier mode; a multiplexer to select the unequally weighted partial products in the first multiplier mode and to select the equally weighted partial products in the second multiplier mode; and a carry save adder array configured to combine the selected partial products in the first multiplier mode and in the second multiplier mode.Type: ApplicationFiled: January 10, 2008Publication date: August 14, 2008Applicant: Analog Devices, Inc.Inventors: Andreas D. Olofsson, Baruch Yanovitch