Abstract: Embodiments of the present invention provide a computer program product for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.

Abstract: Embodiments of the present invention provide computer system for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.

Abstract: Embodiments include a system, apparatus, and method for ESD power clamps. Aspects include protecting a circuit using an ESD power clamp device. The ESD power clamp device includes a trigger circuit having a resistor-capacitor network and an inverter stage circuit, wherein the trigger circuit is configured to detect an ESD event. Aspects of the invention further include a timing circuit coupled to the trigger circuit and a timing controlled transistor, wherein the timing circuit controls the timing controlled transistor to prevent the capacitor in the RC network from charging when the timing circuit is initiated. Aspects also include a clamp transistor coupled to the trigger circuit, wherein the clamp transistor is controlled by a signal received from the trigger circuit, and a timing controlled transistor coupled to the trigger circuit and the timing circuit, where the timing controlled transistor switches states based on the output of the timing circuit.

Abstract: Embodiments include a system, apparatus, and method for ESD power clamps. Aspects include protecting a circuit using an ESD power clamp device. The ESD power clamp device includes a trigger circuit having a resistor-capacitor network and an inverter stage circuit, wherein the trigger circuit is configured to detect an ESD event. Aspects of the invention further include a timing circuit coupled to the trigger circuit and a timing controlled transistor, wherein the timing circuit controls the timing controlled transistor to prevent the capacitor in the RC network from charging when the timing circuit is initiated. Aspects also include a clamp transistor coupled to the trigger circuit, wherein the clamp transistor is controlled by a signal received from the trigger circuit, and a timing controlled transistor coupled to the trigger circuit and the timing circuit, where the timing controlled transistor switches states based on the output of the timing circuit.

Abstract: Embodiments of the present invention provide methods for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection structures for eFuses. The structure includes an electrostatic discharge (ESD) protection structure operatively coupled to an eFuse, which is structured to prevent unintentional programming of the eFuse due to an ESD event originating at a source.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection structures for eFuses. The structure includes an electrostatic discharge (ESD) protection structure operatively coupled to an eFuse, which is structured to prevent unintentional programming of the eFuse due to an ESD event originating at a source.

Abstract: Disclosed is an integrated circuit (IC) chip incorporating a temperature-sensitive element and temperature stabilization circuitry for ensuring that the temperature of the temperature-sensitive element (TSE) remains essentially constant. The IC chip comprises a temperature-sensitive element and, within at least one region adjacent to the temperature-sensitive element, a first circuit that radiates a first heat amount to the TSE and a second circuit that radiates a second heat amount to the TSE. The second circuit senses changes in a first current amount in the first circuit and, thereby changes in the first heat amount. In response to those changes, the second circuit also automatically adjusts a second current amount in the second circuit and, thereby the second heat amount in order to ensure that the total heat amount radiated by the first circuit and the second circuit, in combination, to the TSE remains constant. Also disclosed is an associated method.

Abstract: Embodiments include a system, apparatus, and method for ESD power clamps. Aspects include protecting a circuit using an ESD power clamp device. The ESD power clamp device includes a trigger circuit having a resistor-capacitor network and an inverter stage circuit, wherein the trigger circuit is configured to detect an ESD event. Aspects of the invention further include a timing circuit coupled to the trigger circuit and a timing controlled transistor, wherein the timing circuit controls the timing controlled transistor to prevent the capacitor in the RC network from charging when the timing circuit is initiated. Aspects also include a clamp transistor coupled to the trigger circuit, wherein the clamp transistor is controlled by a signal received from the trigger circuit, and a timing controlled transistor coupled to the trigger circuit and the timing circuit, where the timing controlled transistor switches states based on the output of the timing circuit.

Abstract: A magneto-resistive (MR) sensor protection circuit is disclosed, for the protection of an MR sensor. The MR sensor may have a safe operating voltage range, a normal operating voltage range within the safe operating voltage range, and two terminals coupled to a read channel circuit, including a positive terminal and a negative terminal. The MR sensor protection circuit may have positive and negative protection threshold voltage ranges. The MR sensor protection circuit may also have a plurality of N-channel field-effect transistors (NFETs) that are coupled to the positive terminal and to the negative terminal, and configured to, in response to a voltage between the two terminals being within either the positive or the negative protection threshold voltage range, limit the voltage between the terminals by shunting current between the positive terminal and the negative terminal.

Abstract: Disclosed is an integrated circuit (IC) chip incorporating a temperature-sensitive element and temperature stabilization circuitry for ensuring that the temperature of the temperature-sensitive element (TSE) remains essentially constant. The IC chip comprises a temperature-sensitive element and, within at least one region adjacent to the temperature-sensitive element, a first circuit that radiates a first heat amount to the TSE and a second circuit that radiates a second heat amount to the TSE. The second circuit senses changes in a first current amount in the first circuit and, thereby changes in the first heat amount. In response to those changes, the second circuit also automatically adjusts a second current amount in the second circuit and, thereby the second heat amount in order to ensure that the total heat amount radiated by the first circuit and the second circuit, in combination, to the TSE remains constant. Also disclosed is an associated method.

Abstract: A magneto-resistive (MR) sensor protection circuit is disclosed, for the protection of an MR sensor. The MR sensor may have a safe operating voltage range, a normal operating voltage range within the safe operating voltage range, and two terminals coupled to a read channel circuit, including a positive terminal and a negative terminal. The MR sensor protection circuit may have positive and negative protection threshold voltage ranges. The MR sensor protection circuit may also have a plurality of N-channel field-effect transistors (NFETs) that are coupled to the positive terminal and to the negative terminal, and configured to, in response to a voltage between the two terminals being within either the positive or the negative protection threshold voltage range, limit the voltage between the terminals by shunting current between the positive terminal and the negative terminal.

Abstract: Circuits for programming an electrical fuse, methods for programming an electrical fuse, and methods for designing a silicon-controlled rectifier for use in programming an electrical fuse. A programming current for the electrical fuse is directed through the electrical fuse and the silicon-controlled rectifier. Upon reaching a programmed resistance value for the electrical fuse, the silicon-controlled rectifier switches from a low-impedance state to a high-impedance state that interrupts the programming current.

Abstract: Circuits for programming an electrical fuse, methods for programming an electrical fuse, and methods for designing a silicon-controlled rectifier for use in programming an electrical fuse. A programming current for the electrical fuse is directed through the electrical fuse and the silicon-controlled rectifier. Upon reaching a programmed resistance value for the electrical fuse, the silicon-controlled rectifier switches from a low-impedance state to a high-impedance state that interrupts the programming current.

Abstract: A method of designing, for a magneto-resistive (MR) sensor, a protection circuit having a first and a second N-channel field-effect transistor (NFET) and at least one positive-negative (PN) diode is disclosed. The method may include determining a safe operating voltage range for the MR sensor and determining, within the safe operating voltage range, a normal operating voltage range for the MR sensor. The method may also include determining a protection threshold voltage range outside of the normal operating voltage range and within the safe operating voltage range of the MR sensor. The method may also include selecting device parameters to configure the first and second NFETs and the at least one PN diode to, in response to a voltage applied to the MR sensor being within a protection threshold voltage range, limit, by shunting current, the voltage applied to the MR sensor.

Abstract: A method of designing, for a magneto-resistive (MR) sensor, a protection circuit having a first and a second N-channel field-effect transistor (NFET) and at least one positive-negative (PN) diode is disclosed. The method may include determining a safe operating voltage range for the MR sensor and determining, within the safe operating voltage range, a normal operating voltage range for the MR sensor. The method may also include determining a protection threshold voltage range outside of the normal operating voltage range and within the safe operating voltage range of the MR sensor. The method may also include selecting device parameters to configure the first and second NFETs and the at least one PN diode to, in response to a voltage applied to the MR sensor being within a protection threshold voltage range, limit, by shunting current, the voltage applied to the MR sensor.

Abstract: Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

Abstract: A magneto-resistive (MR) sensor protection circuit is disclosed, for the protection of an MR sensor. The MR sensor may have a safe operating voltage range, a normal operating voltage range within the safe operating voltage range, and two terminals coupled to a read channel circuit, including a positive terminal and a negative terminal. The MR sensor protection circuit may have positive and negative protection threshold voltage ranges. The MR sensor protection circuit may also have a plurality of N-channel field-effect transistors (NFETs) that are coupled to the positive terminal and to the negative terminal, and configured to, in response to a voltage between the two terminals being within either the positive or the negative protection threshold voltage range, limit the voltage between the terminals by shunting current between the positive terminal and the negative terminal.

Abstract: Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

Abstract: Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.