Patents by Inventor Andreas Due Engh-Halstvedt

Andreas Due Engh-Halstvedt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250111576
    Abstract: When preparing and storing primitive lists in a tile-based graphics processing system, one or more primitive list pointer arrays store pointers, each pointer indicating a location in storage of one or more of the primitive lists. A further pointer array stores further pointers, each further pointer indicating a location in storage of one or more of the primitive list pointer arrays.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Arm Limited
    Inventors: Rafal Stepuch, Andreas Due Engh-Halstvedt, Frank Klaeboe Langtind
  • Publication number: 20250111463
    Abstract: When generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks from different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks for the different render outputs are enforced.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Arm Limited
    Inventors: Olof Henrik Uhrenholt, Andreas Due Engh-Halstvedt, Philip Carlos Garcia, Wing-Tsi Henry Wong, Sandeep Kala, Joseph Michael Richardson
  • Patent number: 12242856
    Abstract: A data processor comprising an execution engine 51 for executing programs for execution threads and one or more caches 48, 49 operable to store data values for use when executing program instructions to perform processing operations for execution threads. The data processor further comprises a thread throttling control unit 54 configured to monitor the operation of the caches 48, 49 during execution of programs for execution threads, and to control the issuing of instructions for execution threads to the execution engine for executing a program based on the monitoring of the operation of the caches during execution of the program.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: March 4, 2025
    Assignee: Arm Limited
    Inventors: Tord Kvestad Øygard, Olof Henrik Uhrenholt, Andreas Due Engh-Halstvedt
  • Publication number: 20240348935
    Abstract: A method of processing data in a graphics processor when performing tile-based rendering in which a render output is sub-divided into a plurality of tiles for rendering. The rendering is performed as two separate processing passes: a first processing pass that sorts primitives into respective regions of the render output and a second processing pass that renders the tiles into which the render output is sub-divided for rendering. During the first processing pass, “tile elimination” data is generated indicative of which of the rendering tiles should be rendered during the second processing pass. The tile elimination data generated in the first processing pass can then be used to control the rendering of tiles during the second processing pass.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 17, 2024
    Applicant: Arm Limited
    Inventors: Daniel Fedai LARSEN, Tord Kvestad ØYGARD, Frank Klaeboe LANGTIND, Andreas Due ENGH-HALSTVEDT
  • Patent number: 12086454
    Abstract: A data processing system includes an external memory system, a processor and an internal memory system. The internal memory system includes an internal memory that stores data for use by the processor when performing data processing operations. The internal memory system also includes a data encoder associated with the internal memory. The data encoder reads data from the external memory system to the data encoder and returns the data to the external memory system from the data encoder, without storing the data in the internal memory.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: September 10, 2024
    Assignee: Arm Limited
    Inventors: Olof Henrik Uhrenholt, Andreas Due Engh-Halstvedt
  • Patent number: 12052508
    Abstract: A method of processing data in a graphics processor when performing tile-based rendering in which a render output is sub-divided into a plurality of tiles for rendering. The rendering is performed as two separate processing passes: a first processing pass that sorts primitives into respective regions of the render output and a second processing pass that renders the tiles into which the render output is sub-divided for rendering. During the first processing pass, “tile elimination” data is generated indicative of which of the rendering tiles should be rendered during the second processing pass. The tile elimination data generated in the first processing pass can then be used to control the rendering of tiles during the second processing pass.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: July 30, 2024
    Assignee: Arm Limited
    Inventors: Daniel Fedai Larsen, Tord Kvestad Øygard, Frank Klaeboe Langtind, Andreas Due Engh-Halstvedt
  • Publication number: 20240193719
    Abstract: A tiled-based graphics processor that comprises a plurality of tiling units is disclosed. The graphics processor includes an assigning circuit that assigns tiling units to process draw calls or draw call parts, and causes assigned tiling units to process draw calls or draw call parts.
    Type: Application
    Filed: November 22, 2023
    Publication date: June 13, 2024
    Applicant: Arm Limited
    Inventors: Frank Klaeboe Langtind, Andreas Due Engh-Halstvedt
  • Publication number: 20240169464
    Abstract: When generating a graphics processing output by assembling a sequence of one or more of primitives to be processed from a set of vertex indices provided for the output based on primitive configuration information provided for the output, one or more vertex packets are generated using the vertex indices for the assembled primitives, each vertex packet comprising a plurality of vertices of the assembled primitives. After a threshold number of vertices have been allocated to a vertex packet, vertex attribute processing for the vertices of the vertex packet is triggered, to thereby generate a vertex packet comprising processed vertex attributes for the vertices of the vertex packet. The assembled primitives and the generated vertex packets are then provided to later stages of the graphics processing pipeline for processing.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 23, 2024
    Applicant: Arm Limited
    Inventors: Frank Klaeboe Langtind, Andreas Due Engh-Halstvedt
  • Publication number: 20240169643
    Abstract: When processing primitives in a tile-based graphics processing system in which a render output is sub-divided into a plurality of tiles for rendering, before a primitive is written to a primitive list corresponding to a region of the render output, it is first written to one or more primitive queues allocated to respective regions of the render output. To write the primitives to primitive lists, primitives are written together from a primitive queue allocated to a region of the render output to the primitive list for that region of the render output, in a single primitive list write cycle.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 23, 2024
    Applicant: Arm Limited
    Inventors: Rafal Stepuch, Frank Klaeboe Langtind, Andreas Due Engh-Halstvedt
  • Publication number: 20240169474
    Abstract: When preparing and storing a primitive list in a tile-based graphics processing system, a first block of memory space is allocated for storing the primitive list. When there is insufficient space in the first block of memory space to store all of the graphics primitives for the primitive list, a next block of memory space to be used for storing the primitive list is allocated for storing the primitive list. An indication of the location in memory of the allocated next block of memory space is written at the beginning of the first block of memory space.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 23, 2024
    Applicant: Arm Limited
    Inventors: Andreas Due Engh-Halstvedt, Frank Klaeboe Langtind
  • Publication number: 20240168804
    Abstract: The present disclosure relates to a processing resource for a graphics processing system for performing graphics processing for an application executing on a host processor of the graphics processing system according to a command stream, the command stream being generated by the host processor in response to an API call from the application, the processing resource comprising: a control circuit configured to execute commands from the command stream, wherein the command stream comprises one or more commands relating to a processing task and one or more commands relating to at least one state group associated with the processing task; at least one processing circuit configured to perform processing tasks; a shadow state storage module configured for use by the control circuit to store state information; and a processing state storage module configured for use by the processing circuit to store state information, wherein the control circuit is configured to determine one or more changed states within the at leas
    Type: Application
    Filed: October 20, 2023
    Publication date: May 23, 2024
    Applicant: Arm Limited
    Inventors: Maochang Dang, Andreas Due Engh-Halstvedt, Andreas Danner Nilsen, Brian Gordon Pearson, Espen Amodt
  • Publication number: 20230388651
    Abstract: A method of processing data in a graphics processor when performing tile-based rendering in which a render output is sub-divided into a plurality of tiles for rendering. The rendering is performed as two separate processing passes: a first processing pass that sorts primitives into respective regions of the render output and a second processing pass that renders the tiles into which the render output is sub-divided for rendering. During the first processing pass, “tile elimination” data is generated indicative of which of the rendering tiles should be rendered during the second processing pass. The tile elimination data generated in the first processing pass can then be used to control the rendering of tiles during the second processing pass.
    Type: Application
    Filed: May 25, 2023
    Publication date: November 30, 2023
    Inventors: Daniel Fedai LARSEN, Tord Kvestad ØYGARD, Frank Klaeboe LANGTIND, Andreas Due ENGH-HALSTVEDT
  • Patent number: 11789867
    Abstract: A data processing system includes a cache system configured to transfer data stored in the memory system to a processor and to transfer data from the processor to the memory system. The cache system comprises a cache and a data encoder associated with the cache that is configured to encode uncompressed data from the cache for storing in the memory system in a compressed format, and decode compressed data from the memory system for storing in the cache in an uncompressed format.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: October 17, 2023
    Assignee: Arm Limited
    Inventors: Olof Henrik Uhrenholt, Andreas Due Engh-Halstvedt
  • Patent number: 11790479
    Abstract: When generating a graphics processing output, a sequence of one or more of primitives to be processed when generating the output is assembled from a set of vertex indices provided for the output based on primitive configuration information provided for the output, each assembled primitive of the sequence of assembled primitives comprising an identifier for the primitive and a set of one or more vertex indices for the primitive. One or more attributes for vertices of the assembled primitives are then shaded and fetched based on the vertex indices of the assembled primitives. The assembled primitives including their shaded fetched vertex attribute(s) are then provided to later stages of the graphics processing pipeline for processing.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: October 17, 2023
    Assignee: Arm Limited
    Inventors: Frank Klaeboe Langtind, Andreas Due Engh-Halstvedt
  • Publication number: 20230305963
    Abstract: A data processor, such as a graphics processor, is disclosed. The data processor includes a set of one or more counters, and a control circuit that maintains a cache-like pool of corresponding entries. In response to a request for a counter, the control circuit may allocate an entry of the cache-like pool to thereby allocate a counter of the set.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 28, 2023
    Inventors: Andreas Due ENGH-HALSTVEDT, Philip Michael WATTS
  • Patent number: 11734869
    Abstract: A method of operating a graphics processor that executes a graphics processing pipeline comprising a vertex shading stage is disclosed. A set of blocks of memory space that may be represented by a linked list is provided and memory space for storing vertex shaded attribute data generated by the vertex shading stage is allocated from one of the blocks of memory space in the set of blocks of memory space. When data stored in a block of memory space is no longer needed by the graphics processing pipeline, the block can be “recycled” for use by the pipeline.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: August 22, 2023
    Assignee: Arm Limited
    Inventors: Andreas Due Engh-Halstvedt, Frank Klaeboe Langtind, Mark Underwood
  • Patent number: 11625332
    Abstract: In a data processing system comprising a cache system configured to transfer data stored in a memory system to a processor and vice-versa, a processing unit operable to read data from a cache of the cache system can send a read request for data to the cache. The cache system, in response to the read request, determines whether the requested data is present in the cache. When the requested data is present in the cache, the cache system returns the data from the cache to the processing unit and invalidates the entry for the data in the cache. When the requested data is not present in the cache, the cache system returns an indication of that to the processing unit, without the cache system sending a request for the data towards the memory system.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: April 11, 2023
    Assignee: Arm Limited
    Inventors: Olof Henrik Uhrenholt, Andreas Due Engh-Halstvedt
  • Publication number: 20220382587
    Abstract: A data processing system is disclosed that includes one or more processors that can perform producer processes to produce work and consumer processes that can consume work produced by a producer process. The system includes a pool of plural communication resources that may be used for communications between a producer process and a consumer process. The system tracks the usage of communication resources of the pool of communication resources, and allocates a communication resource from the pool of communication resources based on the tracking.
    Type: Application
    Filed: March 28, 2022
    Publication date: December 1, 2022
    Applicant: Arm Limited
    Inventors: Andreas Danner Nilsen, Mark Underwood, Arne Aas, Andreas Due Engh-Halstvedt, Shan Wu
  • Publication number: 20220308884
    Abstract: A data processor comprising an execution engine 51 for executing programs for execution threads and one or more caches 48, 49 operable to store data values for use when executing program instructions to perform processing operations for execution threads. The data processor further comprises a thread throttling control unit 54 configured to monitor the operation of the caches 48, 49 during execution of programs for execution threads, and to control the issuing of instructions for execution threads to the execution engine for executing a program based on the monitoring of the operation of the caches during execution of the program.
    Type: Application
    Filed: March 24, 2022
    Publication date: September 29, 2022
    Inventors: Tord Kvestad Øygard, Olof Henrik Uhrenholt, Andreas Due Engh-Halstvedt
  • Publication number: 20220245751
    Abstract: When generating a graphics processing output, a sequence of one or more of primitives to be processed when generating the output is assembled from a set of vertex indices provided for the output based on primitive configuration information provided for the output, each assembled primitive of the sequence of assembled primitives comprising an identifier for the primitive and a set of one or more vertex indices for the primitive. One or more attributes for vertices of the assembled primitives are then shaded and fetched based on the vertex indices of the assembled primitives. The assembled primitives including their shaded fetched vertex attribute(s) are then provided to later stages of the graphics processing pipeline for processing.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 4, 2022
    Applicant: Arm Limited
    Inventors: Frank Klaeboe Langtind, Andreas Due Engh-Halstvedt