Patents by Inventor Andreas Due Engh-Halstvedt

Andreas Due Engh-Halstvedt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10733782
    Abstract: To perform a graphics processing operation for the entirety of an area of a render output being generated by a graphics processor, a command to draw a primitive occupying the entire area of the render output is issued to the graphics processor. The graphics processor draws the primitive by determining the vertices to use for the primitive from the area of the render output. In a tile-based graphics processor at least, the graphics processor in an embodiment also determines whether it is unnecessary to process the graphics processing command for a rendering tile and when it is determined that processing the graphics processing command for the rendering tile is unnecessary, the graphics processor omits processing the graphics processing command for the rendering tile.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: August 4, 2020
    Assignee: Arm Limited
    Inventors: Frode Heggelund, Andreas Due Engh-Halstvedt, Christian Vik Grovdal
  • Patent number: 10706607
    Abstract: When a graphics texture mapping apparatus is to perform a texture filtering operation that uses the data values of a plurality of texels, the texture mapper first determines whether any of the data values of the texels to be used for the texture filtering operation are the same, and then selects a texture filtering operation to be performed using data values of the texels based on the determination. The texture mapper then performs the selected texture filtering operation using one or more of the data values of the texels to provide the required texture filtering operation output result.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: July 7, 2020
    Assignee: Arm Limited
    Inventors: Peter William Harris, Edvard Fielding, Andreas Due Engh-Halstvedt, Lukasz Kulasza
  • Patent number: 10650580
    Abstract: A graphics processing pipeline includes: a position shader, a tiler, a pool of memory for storing primitive lists and vertex shaded attributes data for vertices, a varying-only vertex shader, and a fragment frontend and shader. The position shader performs vertex shading for the positional attributes of the vertices of a set of vertices to be processed by the graphics processing pipeline. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output. When the tiler determines that a vertex should be processed further to generate the render output, it allocates memory space in the memory pool for storing vertex shaded attributes data for the vertex. Vertex shaded attributes data for the vertex is then stored in the allocated space in the memory pool for later use, e.g., by the fragment frontend and shader.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: May 12, 2020
    Assignee: Arm Limited
    Inventors: Andreas Due Engh-Halstvedt, Frank Klaeboe Langtind
  • Patent number: 10650577
    Abstract: A tile-based graphics processing pipeline includes a back-facing determination and culling unit that is operable to cull back-facing triangles before the tiling stage. The back-facing determination and culling unit include a triangle size estimator that estimates the size of a triangle being considered. If the size of the triangle is less than a selected size, then the area of the triangle is calculated using fixed point arithmetic and the result of that area calculation is used by a back-face culling unit to determine whether to cull the triangle or not. On the other hand, if the size estimator determines that the primitive is greater than the selected size, then the triangle bypasses the fixed point area calculation and back-face culling unit and is instead passed directly to the tiler.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: May 12, 2020
    Assignee: ARM LTD
    Inventors: Andreas Due Engh-Halstvedt, Frank Langtind
  • Publication number: 20200111247
    Abstract: To perform a graphics processing operation for the entirety of an area of a render output being generated by a graphics processor, a command to draw a primitive occupying the entire area of the render output is issued to the graphics processor. The graphics processor draws the primitive by determining the vertices to use for the primitive from the area of the render output. In a tile-based graphics processor at least, the graphics processor in an embodiment also determines whether it is unnecessary to process the graphics processing command for a rendering tile and when it is determined that processing the graphics processing command for the rendering tile is unnecessary, the graphics processor omits processing the graphics processing command for the rendering tile.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 9, 2020
    Applicant: Arm Limited
    Inventors: Frode Heggelund, Andreas Due Engh-Halstvedt, Christian Vik Grovdal
  • Patent number: 10607400
    Abstract: A graphics processing pipeline comprises vertex shading circuitry that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline, to generate, inter alia, a separate vertex shaded position attribute value for each view of the plural different views. Tiling circuitry then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. Vertex shading circuitry then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further, to generate, inter alia, a single vertex shaded attribute value for the set of plural views.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 31, 2020
    Assignee: Arm Limited
    Inventors: Sandeep Kakarlapudi, Jorn Nystad, Andreas Due-Engh Halstvedt
  • Patent number: 10599584
    Abstract: When writing data to memory via a write buffer including a write cache containing a plurality of lines for storing data to be written to memory and an address-translation cache that stores a list of virtual address to physical address translations, a record of a set of lines of the write cache that are available to be evicted to the memory is maintained, and the evictable lines in the record of evictable lines are processed by requesting from the address-translation cache a respective physical address for each virtual address associated with an evictable line. The address-translation cache returns a hit or a miss status to the write buffer for each evictable line that is checked, and the write buffer writes out to memory at least one of the evictable lines for which a hit status was returned.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: March 24, 2020
    Assignee: Arm Limited
    Inventors: Andreas Due Engh-Halstvedt, Frank Langtind, Shareef Justin Jalloq
  • Patent number: 10580113
    Abstract: A tile-based graphics processing system comprises a graphics processing pipeline comprising a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasteriser to generate rendered fragment data, and a tile buffer configured to store data locally to the graphics processing pipeline. The graphics processing system is operable to cause data for use when performing graphics processing operations for each tile of a set of plural tiles of a plurality of tiles to be loaded into the tile buffer before causing graphics processing operations to be performed for any of the tiles of the set of plural tiles.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 3, 2020
    Assignee: Arm Limited
    Inventors: Lars Oskar Flordal, Toni Viki Brkic, Christian Vik Grovdal, Andreas Due Engh-Halstvedt, Frode Heggelund
  • Publication number: 20200057636
    Abstract: Processing circuitry performs processing operations specified by program instructions. An instruction decoder decodes an atomic-add-with-carry instruction AADDC to control the processing circuitry to perform an atomic operation of an add of an addend operand value and a data value stored in a memory to generate a result value stored in the memory and a carry value indicative of whether or not the add generated a carry out. The atomic-add-with-carry instructions may be used within systems which accumulate a local sum value prior to a data value being returned into a local cache memory at which time the local sum value is added to the return data value. The atomic-add-with-carry instructions may also be used in embodiments comprising a coalescing tree of respective processing apparatus where the carry out values generated from local sums produced at each node are returned early to higher nodes within the hierarchy thereby releasing them to commence other processing.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventor: Andreas Due ENGH-HALSTVEDT
  • Patent number: 10430099
    Abstract: A data array to be stored is first divided into a plurality of blocks. Each block is further sub-divided into a set of sub-blocks. Data representing sub-blocks of the data array is stored, together with a header data block for each block that the data array has been divided into. For each block, it is determined whether all the data positions for the block have the same data value associated with them, and, if so, an indication that all of the data positions within the block have the same data value associated with them, and an indication of the same data value that is associated with each of the data positions in the block, is stored in the header data block for that block of the data array.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 1, 2019
    Assignee: Arm Limited
    Inventors: Quinn Carter, Lars Oskar Flordal, Jakob Axel Fries, Andreas Due Engh-Halstvedt
  • Patent number: 10388057
    Abstract: In a graphics processing system, when using a graphics texture that is stored in memory as YUV texture data, the YUV texture data is stored in the texture cache from which it is to be read when generating a render output such that the data values for a chrominance data element and its associated set of one or more luminance data elements of the texture are stored together as a group in the cache. The group of data in the cache is tagged with an identifier for the data values of the chrominance data element and its associated set of one or more luminance data elements that is useable to identify the chrominance data element and its associated set of one or more luminance data elements in the cache, and that is indicative of a position in the YUV graphics texture.
    Type: Grant
    Filed: July 8, 2018
    Date of Patent: August 20, 2019
    Assignee: Arm Limited
    Inventors: Edvard Fielding, Jorn Nystad, Andreas Due Engh-Halstvedt
  • Patent number: 10331404
    Abstract: Apparatus for processing data includes processing circuitry 16, 18, 20, 22, 24, 26 and decoder circuitry 14 for decoding program instructions. The program instructions decoded include a floating point pre-conversion instruction which performs round-to-nearest ties to even rounding upon the mantissa field of an input floating number to generate an output floating point number with the same mantissa length but with the mantissa rounded to a position corresponding to a shorter mantissa field. The output mantissa field includes a suffix of zero values concatenated the rounded value. The decoder for circuitry 14 is also responsive to an integer pre-conversion instruction to quantise and input integer value using round-to-nearest ties to even rounding to form an output integer operand with a number of significant bits matched to the mantissa size of a floating point number to which the integer is later to be converted using an integer-to-floating point conversion instruction.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: June 25, 2019
    Assignee: ARM Limited
    Inventors: Jorn Nystad, Andreas Due Engh-Halstvedt, Simon Alex Charles
  • Publication number: 20190138458
    Abstract: When writing data to memory via a write buffer including a write cache containing a plurality of lines for storing data to be written to memory and an address-translation cache that stores a list of virtual address to physical address translations, a record of a set of lines of the write cache that are available to be evicted to the memory is maintained, and the evictable lines in the record of evictable lines are processed by requesting from the address-translation cache a respective physical address for each virtual address associated with an evictable line. The address-translation cache returns a hit or a miss status to the write buffer for each evictable line that is checked, and the write buffer writes out to memory at least one of the evictable lines for which a hit status was returned.
    Type: Application
    Filed: November 7, 2017
    Publication date: May 9, 2019
    Applicant: Arm Limited
    Inventors: Andreas Due Engh-Halstvedt, Frank Langtind, Shareef Justin Jalloq
  • Publication number: 20190108610
    Abstract: A tile-based graphics processing system comprises a graphics processing pipeline comprising a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasteriser to generate rendered fragment data, and a tile buffer configured to store data locally to the graphics processing pipeline. The graphics processing system is operable to cause data for use when performing graphics processing operations for each tile of a set of plural tiles of a plurality of tiles to be loaded into the tile buffer before causing graphics processing operations to be performed for any of the tiles of the set of plural tiles.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 11, 2019
    Applicant: Arm Limited
    Inventors: Lars Oskar Flordal, Toni Viki Brkic, Christian Vik Grovdal, Andreas Due Engh-Halstvedt, Frode Heggelund
  • Patent number: 10255718
    Abstract: A graphics processing pipeline includes position shading circuitry, a tiler, varying-only vertex shading circuitry and fragment (frontend) shading circuitry. The tiler reads a list of indices defining a set of vertices to be processed by the graphics processing pipeline and determines whether or not vertex shading is required for the positional attributes of the vertices. If vertex shading is required, the tiler sends a position shading request for the vertices to the position shading circuitry. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output and that accordingly should be subjected to a second, varying shading, vertex shading operation. When the tiler determines that a vertex (or group of vertices) should be subjected to the second, varying shading, vertex shading operation, the tiler sends a varying shading request for the vertex (or vertices) to the varying shading circuitry.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 9, 2019
    Assignee: Arm Limited
    Inventors: Frank Langtind, Andreas Due Engh-Halstvedt, Sandeep Kakarlapudi
  • Publication number: 20190079867
    Abstract: Cache storage comprising cache lines, each configured to store respective data entries. The cache storage is configured to store a tag in the form of: an individual tag portion which is individual to a cache line; a shareable tag portion which is shareable between cache lines; and pointer data which associates an individual tag portion with a shareable tag portion.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 14, 2019
    Inventors: Antonio GARCÍA GUIRADO, Andreas Due ENGH-HALSTVEDT
  • Patent number: 10216479
    Abstract: An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions. A convert and accumulate instruction is provided, and the decoder circuitry is responsive to decoding the convert and accumulate instruction to generate one or more control signals to control the execution circuitry to convert at least one floating-point operand identified by the convert and accumulate instruction into a corresponding N-bit fixed-point operand having M fraction bits, where M is less than N and M is dependent on a format of the floating-point operand. The execution circuitry accumulates each corresponding N bit fixed-point operand and a P bit fixed-point operand identified by the convert and accumulate instruction in order to generate a P bit fixed-point result value, where P is greater than N and also has M fraction bits.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: February 26, 2019
    Assignee: ARM LIMITED
    Inventors: David Raymond Lutz, Neil Burgess, Christopher Neal Hinds, Andreas Due Engh-Halstvedt
  • Patent number: 10186069
    Abstract: A graphics processing system groups plural initial pilot shader programs into a set of initial pilot shader programs and associates the set of initial pilot shader programs with a set of indexes. The initial pilot shader programs each contain constant program expressions to be executed on behalf of an original shader program. The index for an initial pilot shader program is then used to obtain the instructions contained in the initial pilot shader program for executing the constant program expressions of the initial pilot shader program. The threads for executing a subset of the initial pilot shader programs are also grouped into a thread group and the threads of the thread group are executed in parallel. The graphics processing system provides for efficient preparation and execution of plural initial pilot shader programs.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: January 22, 2019
    Assignee: Arm Limited
    Inventors: Alexander Galazin, Jörg Wagner, Andreas Due Engh-Halstvedt
  • Publication number: 20190019323
    Abstract: In a graphics processing system, when using a graphics texture that is stored in memory as YUV texture data, the YUV texture data is stored in the texture cache from which it is to be read when generating a render output such that the data values for a chrominance data element and its associated set of one or more luminance data elements of the texture are stored together as a group in the cache. The group of data in the cache is tagged with an identifier for the data values of the chrominance data element and its associated set of one or more luminance data elements that is useable to identify the chrominance data element and its associated set of one or more luminance data elements in the cache, and that is indicative of a position in the YUV graphics texture.
    Type: Application
    Filed: July 8, 2018
    Publication date: January 17, 2019
    Applicant: Arm Limited
    Inventors: Edvard Fielding, Jorn Nystad, Andreas Due Engh-Halstvedt
  • Publication number: 20190012829
    Abstract: A graphics processing pipeline includes: a position shader, a tiler, a pool of memory for storing primitive lists and vertex shaded attributes data for vertices, a varying-only vertex shader, and a fragment frontend and shader. The position shader performs vertex shading for the positional attributes of the vertices of a set of vertices to be processed by the graphics processing pipeline. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output. When the tiler determines that a vertex should be processed further to generate the render output, it allocates memory space in the memory pool for storing vertex shaded attributes data for the vertex. Vertex shaded attributes data for the vertex is then stored in the allocated space in the memory pool for later use, e.g., by the fragment frontend and shader.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 10, 2019
    Applicant: Arm Limited
    Inventors: Andreas Due Engh-Halstvedt, Frank Klaeboe Langtind