Patents by Inventor Andreas Duevel

Andreas Duevel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10256286
    Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 9, 2019
    Assignee: INTEL CORPORATION
    Inventors: Andreas Duevel, Telesphor Kamgaing, Valluri R. Rao, Uwe Zillmann
  • Patent number: 9881990
    Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: January 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Andreas Duevel, Telesphor Kamgaing, Valluri R. Rao, Uwe Zillmann
  • Publication number: 20170309700
    Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.
    Type: Application
    Filed: May 8, 2017
    Publication date: October 26, 2017
    Inventors: Andreas DUEVEL, Telesphor KAMGAING, Valluri R. RAO, Uwe ZILLMANN
  • Patent number: 9673268
    Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: June 6, 2017
    Assignee: INTEL CORPORATION
    Inventors: Andreas Duevel, Telesphor Kamgaing, Valluri R. Rao, Uwe Zillmann
  • Publication number: 20160276424
    Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.
    Type: Application
    Filed: May 31, 2016
    Publication date: September 22, 2016
    Inventors: Andreas DUEVEL, Telesphor KAMGAING, Valluri R. RAO, Uwe ZILLMANN
  • Patent number: 9229466
    Abstract: A voltage regulator for one or more dies in a multi-stack integrated circuit includes an inductor located on a die, a voltage controller that is electrically coupled to the inductor and is also located on the die, and a capacitor that is electrically coupled to the inductor and the voltage controller and is also located on the die. The inductor defines an interior space and the voltage controller and the capacitor are located within the interior space of the inductor. The inductor can be a lateral inductor or a through layer via inductor. The multi-stack integrated circuit may have multiple dies. A voltage controller may be electrically coupled to each of the dies, although it may be located on only one of the dies. Alternatively, separate voltage controllers may be electrically coupled to each of the multiple dies and may be located on each of the respective dies.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: January 5, 2016
    Assignee: Intel Corporation
    Inventors: Ruchir Saraswat, Andre Schaefer, Uwe Zillman, Andreas Duevel, Valluri Rao, Telesphor Kamgaing, Harish Krishnamurthy
  • Publication number: 20140027880
    Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.
    Type: Application
    Filed: December 29, 2011
    Publication date: January 30, 2014
    Inventors: Andreas Duevel, Telesphor Kamgaing, Valluri R. Rao, Uwe Zillmann
  • Publication number: 20130335059
    Abstract: A voltage regulator for one or more dies in a multi-stack integrated circuit includes an inductor located on a die, a voltage controller that is electrically coupled to the inductor and is also located on the die, and a capacitor that is electrically coupled to the inductor and the voltage controller and is also located on the die. The inductor defines an interior space and the voltage controller and the capacitor are located within the interior space of the inductor. The inductor can be a lateral inductor or a through layer via inductor. The multi-stack integrated circuit may have multiple dies. A voltage controller may be electrically coupled to each of the dies, although it may be located on only one of the dies. Alternatively, separate voltage controllers may be electrically coupled to each of the multiple dies and may be located on each of the respective dies.
    Type: Application
    Filed: December 31, 2011
    Publication date: December 19, 2013
    Applicant: Intel Corporation
    Inventors: Ruchir Saraswat, Andre Schaefer, Uwe Zillman, Andreas Duevel, Valluri Rao, Telesphor Kamgaing, Harish Krishnamurthy