Abstract: A method of operating a graphics processor to process sets of geometry to generate an output. Each set of geometry is associated with lower level geometry including vertex data to be used when rendering the geometry as well a separate higher level representation of the geometry. The higher level representations of the geometry can be obtained by the graphics processor independently of the other, lower level geometry and used to determine which sets of geometry should be processed for which regions of the output. Once this determination is made, the regions can be rendered by obtaining and processing the lower level geometry accordingly.

Abstract: When performing foveated rendering, a graphics processor is controlled to render plural, e.g. three, different resolution versions from the same viewpoint for a scene. The rendered different resolution images are then appropriately combined (composited) to provide the output “foveated” image (output frame) that is displayed. The geometry for the scene is processed and sorted into lists for respective rendering tiles of the images being rendered only once, to provide a single set of tile geometry lists that are then used in common when rendering each respective resolution image.

Abstract: A microprocessor system (1) includes a host processor (2), a graphics processing unit (GPU) (3) that includes a number of processing cores (4), and an exception handler. When a thread that is executing on a processing core (4) encounters an exception in its instruction sequence, the thread is redirected to the exception handler. However, the exception event is also communicated to a task manager (5) of the GPU 3. The task manager (5) then broadcasts a cause exception message to each processing core (4). Each processing core then identifies the threads that it is currently executing that the cause exception message relates to, and redirects those threads to the exception handler. In this way, an exception caused by a single thread is broadcast to all threads within a task.

Abstract: A graphics processing system for processing polygons includes a cache with cache lines for storing data entries, each line having a tag for identifying the data stored in the line. The polygons have vertices with which pieces of vertex attribute data are associated. The system also includes processing circuitry which writes, to a line in a first set of lines, data entries associated with pieces of vertex attribute data. The pieces of vertex attribute data are associated with the vertices of a polygon. The processing circuitry also writes a tag including a polygon identifier to identify the polygon associated with the data entries to the line in the first set of lines, and writes, to a second set of lines of the cache, data entries associated with pieces of vertex attribute data. The processing circuitry also writes tags including vertex identifiers to the second set of lines to identify the vertices associated with the data entries.

Abstract: A graphics processing pipeline determines whether respective graphics processing operations, such as respective blends, respective depth tests, etc., to be performed at a stage of the graphics processing pipeline would produce the same result for each sampling point of a set of plural sampling points represented by a fragment being processed by the graphics processing pipeline. If it is determined that respective graphics processing operations would produce the same result for each of the sampling points, then only a single instance of the graphics processing operation is performed and the result of that graphics processing operation is associated with each of the sampling points. The number of instances of the graphics processing operations needed to process the set of plural sampling points which the fragment represents is reduced in comparison to conventional multisampling graphics processing techniques which perform graphics processing operations for fragments on a “per sample” basis.

Abstract: When performing foveated rendering, a graphics processor is controlled to render plural, e.g. three, different resolution versions from the same viewpoint for a scene. The rendered different resolution images are then appropriately combined (composited) to provide the output “foveated” image (output frame) that is displayed. The geometry for the scene is processed and sorted into lists for respective rendering tiles of the images being rendered only once, to provide a single set of tile geometry lists that are then used in common when rendering each respective resolution image.

Abstract: When carrying out a second, higher level of anti-aliasing such as 8×MSAA, in a graphics processing pipeline 1 configured to “natively” support a first level of anti-aliasing, such as 4×MSAA, the rasterization stage 3, early Z (depth) and stencil test stage 4, late Z (depth) and stencil test stage 7, blending stage 9, and downsampling and writeback (multisample resolve) stage 11 of the graphics processing pipeline 1 process each graphics fragment or pixel that they receive for processing in plural processing passes, each such processing pass processing a sub-set of the sampling points that the fragment represents, but the fragment shader 6 is configured to process each graphics fragment in a processing pass that processes all the sampling points that the fragment represents in parallel, so as to ensure compliance with the desired higher level of multisampled anti-aliasing.

Abstract: A graphics processing pipeline (20) comprises first vertex shading circuitry (21) that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline. Tiling circuitry (22) then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. A second vertex shading circuitry (23) then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further.

Abstract: A tile-based graphics processing pipeline 1 comprising a rasteriser 3, a renderer 6, a tile buffer 10, a write out stage 13 and a programmable processing stage 14. The tile buffer 10 stores multiple render targets for a deferred shading operation and the programmable processing stage 14 is operable to, under the control of graphics program instructions, read data from two or more of a set of multiple render targets for a deferred shading operation stored in the tile buffer 10, perform a deferred shading processing operation using the read data, and to write the result of the processing operation to an output render target in the tile buffer 10, or to external memory.

Abstract: A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. Each page of a graphics texture has an associated fade factor value that can be set by an application that is to use the texture to control the contribution that the page will be used to make to any texturing result that is generated using the texture page in question. The graphics processing system then controls the contribution of texture data from a texture page to texturing result data to be generated in accordance with the fade factor value associated with the texture page in question. This allows texture paging to be done in a more visually pleasing manner than just a binary “page-is-here”/“page-is-not-here” switch.

Abstract: A processing system comprises plural processing cores and a task allocator for allocating tasks to the processing cores. The processing cores perform the tasks that are allocated to them so as to produce results for the tasks, the results being stored by the processing cores in a buffer. The task allocator indicates to the processing cores memory portions within the buffer in which to store the results. When the processing cores determine that a given memory portion is becoming full, the processing cores request that the task allocator indicates a new memory portion in which to store its results. The processing system allows the task allocator to dynamically and efficiently allocate memory portions to plural processing cores without the task allocator 40 needing to know the sizes of the results being produced by the processing cores.

Abstract: In a graphics processing pipeline 1, a primitive depth sorting stage 9 is arranged prior to the rasterization stage 3 and rendering stage 6. The primitive depth sorting stage 9 operates to sort successive sub-sets of primitives in a stream of primitives 2 received by the graphics processing pipeline 1 based on their depth values. The so-sorted primitives are then output from the primitive depth sorting stage 9 in their sorted depth order to the rasterizer 3. This makes the depth test stages 4, 13 of the graphics processing pipeline 1 more efficient in their hidden surface removal operations, because the primitives entering the rasterizer 3 will be in depth order.

Abstract: A microprocessor system (1) includes a host processor (2),a graphics processing unit (GPU) (3) that includes a number of processing cores (4), and an exception handler. When a thread that is executing on a processing core (4) encounters an exception in its instruction sequence, the thread is redirected to the exception handler. However, the exception event is also communicated to a task manager (5) of the GPU 3. The task manager (5) then broadcasts a cause exception message to each processing core (4). Each processing core then identifies the threads that it is currently executing that the cause exception message relates to, and redirects those threads to the exception handler. In this way, an exception caused by a single thread is broadcast to all threads within a task.

Abstract: A data processing system includes an execution pipeline that includes one or more programmable execution stages which execute execution threads to execute instructions to perform data processing operations. Instructions to be executed by a group of execution threads are first fetched into an instruction cache and then read from the instruction cache for execution by the thread group. When an instruction to be executed by a thread group is present in a cache line in the instruction cache, or is to be fetched into an allocated cache line in the instruction cache, a pointer to the location of the instruction in the instruction cache is stored for the thread group. This stored pointer is then used to retrieve the instruction for execution by the thread group from the instruction cache.

Abstract: Operating a graphics processing pipeline that includes processing stages including a rasteriser that rasterises input primitives to generate graphics fragments to be processed, each graphics fragment having one or more sampling points associated with it, and a renderer that processes fragments generated by the rasteriser to generate output fragment data for output to a render output, comprising the following steps: (i) determining first information to test whether at least a part of a primitive should be processed further; (ii) using at least some of the first information to decide whether to process at least a part of the primitive further; and if it is decided that at least a part of the primitive is to be processed further: (iii) determining further information to be used in further processing of the primitive; and (iv) further processing at least a part of the primitive using the determined further information.

Abstract: When processing a set of tiles to generate an output in a tile based graphics processing pipeline, the pipeline, for one or more tiles of the set of tiles, renders one or more render targets containing data to be used in a processing operation (602), and stores the render targets in the tile buffer (604). It also stores some but not all of the sampling position values for a render target or targets for use when processing an adjacent tile of the set of tiles (606). It then performs a processing operation for the tile using the stored render target or targets (608) and one or more stored sampling position values from another, adjacent tile of the set of tiles (610), to generate an output for the tile (612).

Abstract: In a tile-based graphics processing system, when an overlay image is to be rendered onto an existing image, the existing tile data for the existing image from the frame buffer in the main memory is pre-loaded into the local color buffer of the graphics processor (step 41). The overlay content is then rendered and used to modify the tile data stored in the color buffer (step 44). When the data for a given sampling position stored in the tile buffer is modified as a result of the overlay image, a corresponding dirty bit for the tile region that the sampling position falls within is set (step 45). Then, when all the rendering for the tile has been completed, the dirty bits are examined to determine which regions of the tile have been modified (step 46). The modified tile regions are written back to the output image in the frame buffer in the main memory (step 47), but any regions whose dirty bits have not been set are not written back to the frame buffer in the main memory.

Abstract: An apparatus for processing data 2 is provided including processing circuitry 24 controlled by an instruction decoder 20 in response to a stream of program instructions. There is also provided dedicated function hardware 12 configured to receive output data from the processing circuitry and to perform a dedicated processing operation. The instruction decoder 20 is responsive to an end instruction 54 and a software processing flag (blend_shade_enabled) to control the processing circuitry to end a current software routine, to generate output data and in dependence upon the software processing flag either trigger processing of the output data by the dedicated function hardware or trigger the processing circuitry to perform a further software routine upon the output data to generate software generated result data instead of hardware generated result data as generated by the dedicated hardware circuitry.

Abstract: A graphics processing system for processing polygons includes a cache with cache lines for storing data entries, each line having a tag for identifying the data stored in the line. The polygons have vertices with which pieces of vertex attribute data are associated. The system also includes processing circuitry which writes, to a line in a first set of lines, data entries associated with pieces of vertex attribute data. The pieces of vertex attribute data are associated with the vertices of a polygon. The processing circuitry also writes a tag including a polygon identifier to identify the polygon associated with the data entries to the line in the first set of lines, and writes, to a second set of lines of the cache, data entries associated with pieces of vertex attribute data. The processing circuitry also writes tags including vertex identifiers to the second set of lines to identify the vertices associated with the data entries.

Abstract: A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. If the texture page that is required for performing a texturing operation at an originally desired level of detail (52) is not present in the local memory of the graphics processing system (53), the virtual texture lookup process loops back to try to sample the texture at an increased level of detail (55), and so on, until texture data that can be used is found in the local memory of the graphics processing system (53). This allows the texturing operation to proceed using texture data for the texel positions in question from a higher level (less detailed) mipmap in place of the originally desired texture data.