Patents by Inventor Andreas G. Andreou

Andreas G. Andreou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10178336
    Abstract: A computational sensing array includes an array of sensing elements. In each sensing element, a first signal is generated from a transducer. A second signal is produced by a collection unit in response to receiving the first signal. The second signal may be modified, in a conditioning unit. A sensing element preprocessing unit generates a word representing the value of the modified second signal, and may produce an indication of change of the first signal. A current value of the word may be stored in a state holding element local to the sensing element, and a previous value of the word may be retained in a further state holding element local to the sensing element.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 8, 2019
    Assignee: The Johns Hopkins University
    Inventors: Charbel G. Rizk, Philippe O. Pouliquen, Andreas G. Andreou, Joseph H. Lin
  • Patent number: 10012534
    Abstract: A photodetection circuit includes an avalanche photodiode and a mode switching circuit that may be configured to selectively switch an operating mode of the photodetection circuit between linear mode and Geiger mode. The photodetection circuit may further include a quenching circuit configured to quench and reset the avalanche photodiode in response to an avalanche event when the photodetection circuit is operated in Geiger mode. The photodetection circuit may additionally include an integration circuit configured to integrate photocurrent output by the photodiode and generate integrated charge units when the photodetection circuit is operated in linear mode. The photodetection circuit may also include a counter configured to count pulses output by the avalanche photodiode when the photodetection circuit is operated in Geiger mode and to count integrated charge units generated by the integration circuit when the photodetection circuit is operated in linear mode.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: July 3, 2018
    Assignee: The Johns Hopkins University
    Inventors: Andreas G. Andreou, Joseph H. Lin, Philippe O. Pouliquen, Charbel G. Rizk
  • Publication number: 20170295337
    Abstract: A computational sensing array includes an array of sensing elements. In each sensing element, a first signal is generated from a transducer. A second signal is produced by a collection unit in response to receiving the first signal. The second signal may be modified, in a conditioning unit. A sensing element preprocessing unit generates a word representing the value of the modified second signal, and may produce an indication of change of the first signal. A current value of the word may be stored in a state holding element local to the sensing element, and a previous value of the word may be retained in a further state holding element local to the sensing element.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 12, 2017
    Inventors: Charbel G. Rizk, Philippe O. Pouliquen, Andreas G. Andreou, Joseph H. Lin
  • Patent number: 9723240
    Abstract: A computational sensing array includes an array of sensing elements. In each sensing element, a first signal is generated from a transducer. A second signal is produced by a collection unit in response to receiving the first signal. The second signal may be modified, in a conditioning unit. A sensing element preprocessing unit generates a word representing the value of the modified second signal, and may produce an indication of change of the first signal. A current value of the word may be stored in a state holding element local to the sensing element, and a previous value of the word may be retained in a further state holding element local to the sensing element.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: August 1, 2017
    Assignee: The Johns Hopkins University
    Inventors: Charbel G. Rizk, Philippe O. Pouliquen, Andreas G. Andreou, Joseph H. Lin
  • Publication number: 20170131143
    Abstract: A photodetection circuit includes an avalanche photodiode and a mode switching circuit that may be configured to selectively switch an operating mode of the photodetection circuit between linear mode and Geiger mode. The photodetection circuit may further include a quenching circuit configured to quench and reset the avalanche photodiode in response to an avalanche event when the photodetection circuit is operated in Geiger mode. The photodetection circuit may additionally include an integration circuit configured to integrate photocurrent output by the photodiode and generate integrated charge units when the photodetection circuit is operated in linear mode. The photodetection circuit may also include a counter configured to count pulses output by the avalanche photodiode when the photodetection circuit is operated in Geiger mode and to count integrated charge units generated by the integration circuit when the photodetection circuit is operated in linear mode.
    Type: Application
    Filed: July 2, 2014
    Publication date: May 11, 2017
    Inventors: Andreas G. Andreou, Joseph H. Lin, Philippe O. Pouliquen, Charbel G. Rizk
  • Patent number: 9274186
    Abstract: A gas cell semiconductor chip assembly includes a gas cell including an alkali gas stored therein and a first semiconductor chip including a first resistive heating loop at a location corresponding to the gas cell to heat the gas cell and a second resistive heating loop around an outer perimeter of the first resistive heating loop. The second resistive heating loop is configured to cancel a magnetic field of the first resistive heating loop based on a current flowing through the first and second resistive heating loops.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 1, 2016
    Assignee: The Johns Hopkins University
    Inventors: Haje Korth, Kim Strohbehn, Andreas G. Andreou, Francisco Tejada
  • Publication number: 20160050382
    Abstract: A computational sensing array includes an array of sensing elements. In each sensing element, a first signal is generated from a transducer. A second signal is produced by a collection unit in response to receiving the first signal. The second signal may be modified, in a conditioning unit. A sensing element preprocessing unit generates a word representing the value of the modified second signal, and may produce an indication of change of the first signal. A current value of the word may be stored in a state holding element local to the sensing element, and a previous value of the word may be retained in a further state holding element local to the sensing element.
    Type: Application
    Filed: October 27, 2015
    Publication date: February 18, 2016
    Inventors: Charbel G. Rizk, Philippe O. Pouliquen, Andreas G. Andreou, Joseph H. Lin
  • Patent number: 9200954
    Abstract: A computational sensing array includes an array of sensing elements. In each sensing element, a first signal is generated from a transducer. A second signal is produced by a collection unit in response to receiving the first signal. The second signal may be modified, in a conditioning unit. A sensing element preprocessing unit generates a word representing the value of the modified second signal, and may produce an indication of change of the first signal. A current value of the word may be stored in a state holding element local to the sensing element, and a previous value of the word may be retained in a further state holding element local to the sensing element.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: December 1, 2015
    Assignee: The Johns Hopkins University
    Inventors: Joseph H. Lin, Philippe O. Pouliquen, Andreas G. Andreou, Charbel G. Rizk
  • Publication number: 20140009149
    Abstract: A gas cell semiconductor chip assembly includes a gas cell including an alkali gas stored therein and a first semiconductor chip including a first resistive heating loop at a location corresponding to the gas cell to heat the gas cell and a second resistive heating loop around an outer perimeter of the first resistive heating loop. The second resistive heating loop is configured to cancel a magnetic field of the first resistive heating loop based on a current flowing through the first and second resistive heating loops.
    Type: Application
    Filed: July 2, 2013
    Publication date: January 9, 2014
    Inventors: Haje Korth, Kim Strohbehn, Andreas G. Andreou, Francisco Tejada
  • Patent number: 8259293
    Abstract: An avalanche photodiode is disclosed. The avalanche photodiode includes a substrate of a first conductivity type. A first well of a second conductivity type is formed within the substrate. A second well of the second conductivity type is formed substantially overlying and extending into the first well. A heavily doped region of the first conductivity type is formed substantially overlying and extending into the first well, the junction between the heavily doped region and the second well forming an avalanche multiplication region. A guard ring is formed from a first conductivity material positioned substantially about the periphery of the multiplication region at least partially underlying the heavily doped region. An outer well ring of the second conductivity type is formed about the perimeter of the deep well and the guard ring.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: September 4, 2012
    Assignee: Johns Hopkins University
    Inventors: Andreas G. Andreou, Miriam Adlerstein Marwick, Philippe O. Pouliquen
  • Publication number: 20100245809
    Abstract: An avalanche photodiode and a sensor array comprising an array of said avalanche photodiodes is disclosed. Then avalanche photodiode comprises a substrate of a first conductivity type; a first well of a second conductivity type formed within the substrate; a second well of the second conductivity type formed substantially overlying and extending into the first well; a heavily doped region of the first conductivity type formed substantially overlying and extending into the first well, the junction between the heavily doped region and the second well forming an avalanche multiplication region; a guard ring formed from a first conductivity material positioned substantially about the periphery of the multiplication region at least partially underlying the heavily doped region; and an outer well ring of the second conductivity type formed about the perimeter of the deep well and the guard ring.
    Type: Application
    Filed: March 17, 2008
    Publication date: September 30, 2010
    Applicant: JOHNS HOPKINS UNIVERSITY
    Inventors: Andreas G. Andreou, Miriam Adlerstein Marwick, Philippe O. Pouliquen
  • Patent number: 6720830
    Abstract: A low-power differential optical receiver useful for high-speed optical communication between CMOS chips includes a multi-stage differential amplifier circuit including a first differential transimpedance stage (22) followed by a plurality of differential feed-forward, high-bandwidth gain stages (24) and a final, differential-to-single-ended converter output stage (26). The inputs of the transimpedance stage receive input signals from a MSM or PIN diode photo-detector. Transistors having plural, different threshold levels are employed within each differential amplifier stage to reduce the size of the footprint of the circuit and improve the gain and bandwidth while decreasing the parasitic capacitance. The optical receiver is fabricated on a silicon on insulator chip, such as in an ultra-thin silicon on sapphire CMOS process which enables the design of high speed circuits with low power consumption and no substrate cross-talk.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: April 13, 2004
    Assignee: Johns Hopkins University
    Inventors: Andreas G. Andreou, Alyssa Apsel
  • Patent number: 6583445
    Abstract: An integrated electronic-optoelectronic module comprising: an ultrathin silicon-on-sapphire composite substrate; at least one electronic device fabricated in the ultrathin silicon; and at least one optoelectronic device bonded to the ultrathin silicon-on-sapphire composite substrate and in electrical communication with the at least one electronic device fabricated in the ultrathin silicon layer. For example, VCSELs and photodetectors are integrated with CMOS electronic circuitry to provide useful modules for electro-optical interconnects for computing and switching systems.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: June 24, 2003
    Assignees: Peregrine Semiconductor Corporation, George Mason University, John Hopkins University, The United States of America as represented by the Secretary of the Army
    Inventors: Ronald E. Reedy, Ravindra A. Athale, George J. Simonis, Andreas G. Andreou, Alyssa Apsel, Zaven Kalayjian, Philippe O. Pouliquen
  • Publication number: 20030025562
    Abstract: A low-power differential optical receiver useful for high-speed optical communication between CMOS chips includes a multi-stage differential amplifier circuit including a first differential transimpedance stage (22) followed by a plurality of differential feed-forward, high-bandwidth gain stages (24) and a final, differential-to-single-ended converter output stage (26). The inputs of the transimpedance stage receive input signals from a MSM or PIN diode photo-detector. Transistors having plural, different threshold levels are employed within each differential amplifier stage to reduce the size of the footprint of the circuit and improve the gain and bandwidth while decreasing the parasitic capacitance. The optical receiver is fabricated on a silicon on insulator chip, such as in an ultra-thin silicon on sapphire CMOS process which enables the design of high speed circuits with low power consumption and no substrate cross-talk.
    Type: Application
    Filed: June 11, 2002
    Publication date: February 6, 2003
    Inventors: Andreas G. Andreou, Alyssa Apsel
  • Patent number: 5206541
    Abstract: A two transistor current-controlled current conveyor (C4) circuit is provided which exploits the translinear properties of the MOS transistor in subthreshold and uses unidirectional current signals. As a result, the circuits of the invention achieve high functionality and integration density with very low power dissipation. Two C4 circuits connected to and communicating through a bidirectional junction circuit of the invention permit the transmission of independent, bidirectional signals. These circuits are useful for implementing synthetic neural systems such as associative memories and silicon retinas, such as winner-takes-all and pyramidal neuron circuits and the outer-plexiform layer of a retina.
    Type: Grant
    Filed: April 30, 1991
    Date of Patent: April 27, 1993
    Assignee: The Johns Hopkins University
    Inventors: Kwabena A. Boahen, Andreas G. Andreou, Philippe O. Pouliquen, Robert E. Jenkins