Abstract: A ferroelectric memory cell architecture in which a pair of cells is fabricated so as to share common elements, and wherein ferroelectric capacitors are fabricated overlying the associated select transistors, thereby achieving a small-area cell architecture. First level refractory metal interconnects formed prior to ferroelectric material deposition steps are utilized with subsequently formed second metallization layers to provide interconnections between the ferroelectric capacitor plates and the underlying transistor regions.

Abstract: A two-transistor, single capacitor ferroelectric memory cell in which a stepped voltage is applied to the drive line for writing polarization states into the capacitor. The isolation transistors are driven into cut off during the intermediate voltage level of the drive line, thereby isolating the ferroelectric capacitor plates with a balanced voltage to enhance full polarization of the ferroelectric domains, irrespective of the polarization state.

Abstract: A sense amplifier that is calibrated prior to each memory read operation to reduce the effects of offsets in a differential input stage. A differential amplifier output signal is connected to a switched inverter by a coupling capacitor. During an equalization time period, the inverter is short circuited between its input and output and is biased to a high gain, trip point. During such time period, the differential amplifier has a bit line input and a reference voltage input, both precharged to a predetermined voltage. The output of the differential amplifier is coupled to a low impedance amplifier. The low impedance amplifier provides an output midway between the supply voltage and ground. The coupling capacitor is charged during the equalization period, but when the bit line voltage and reference voltage are applied to the differential amplifier, the coupling capacitor is charged or discharged, depending upon the state of the memory readout signal.

Abstract: A reference voltage circuit used for determining the polarization state of a ferroelectric capacitor. The circuit includes a pair of ferroelectric capacitors, each polarized to an opposite polarization state. The charge stored in each ferroelectric capacitor is discharged into respective sense capacitors, thereby generating different voltages, each representative of the different polarization states. The sense capacitors are then short circuited together to thereby average the representative voltages and provide a reference voltage that is of intermediate value. The reference voltage can then the used to compare memory cell signals generated by other ferroelectric capacitors to determine the respective polarization states.

Abstract: A ferroelectric programming cell utilizable for providing programming signals for configurable logic elements. A preferred embodiment of the ferroelectric programming cell includes a volatile memory cell having first and second internal data storage nodes that are latched in complementary states when the volatile memory cells positive power input is held to a maximum allowed voltage level and its negative power input is held at ground. A node enabling switching means connected between an external signal generator and the volatile memory cell enables an external signal generator to set the values of the first and second complementary internal nodes. First and second substantially identical capacitance-dividers each include a first ferroelectric capacitance means for storing a non-volatile configuration state.