Patents by Inventor Andreas Georg Nowatzyk

Andreas Georg Nowatzyk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12292473
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.
    Type: Grant
    Filed: December 4, 2023
    Date of Patent: May 6, 2025
    Assignee: Google LLC
    Inventors: Andreas Georg Nowatzyk, Olivier Temam
  • Publication number: 20240256446
    Abstract: Techniques for implementing a hardware-based cache controller in, e.g., a tiered memory computer system are provided. In one set of embodiments, the cache controller can flexibly operate in a number of different modes that aid the OS/hypervisor of the computer system in managing and optimizing its use of the system's memory tiers. In another set of embodiments, the cache controller can implement a hardware architecture that enables it to significantly reduce the probability of tag collisions, decouple cache capacity management from cache lookup and allocation, and handle multiple concurrent cache transactions.
    Type: Application
    Filed: January 26, 2023
    Publication date: August 1, 2024
    Inventors: Andreas Georg Nowatzyk, Pratap Subrahmanyam, Isam Wadih Akkawi, Adarsh Seethanadi Nayak, Nishchay Dua
  • Publication number: 20240256453
    Abstract: Techniques for implementing a hardware-based cache controller in, e.g., a tiered memory computer system are provided. In one set of embodiments, the cache controller can flexibly operate in a number of different modes that aid the OS/hypervisor of the computer system in managing and optimizing its use of the system's memory tiers. In another set of embodiments, the cache controller can implement a hardware architecture that enables it to significantly reduce the probability of tag collisions, decouple cache capacity management from cache lookup and allocation, and handle multiple concurrent cache transactions.
    Type: Application
    Filed: January 26, 2023
    Publication date: August 1, 2024
    Inventors: Andreas Georg Nowatzyk, Pratap Subrahmanyam, Isam Wadih Akkawi, Adarsh Seethanadi Nayak, Nishchay Dua
  • Publication number: 20240256459
    Abstract: A memory hierarchy includes a first memory and a second memory that is at a lower position in the memory hierarchy than the first memory. A method of managing the memory hierarchy includes: observing, over a first period of time, accesses to pages of the first memory; in response to determining that no page in a first group of pages was accessed during the first period of time, moving each page in the first group of pages from the first memory to the second memory; and in response to determining that the number of pages in other groups of pages of the first memory, which were accessed during the first period of time, is less than a threshold number of pages, moving each page in the other group of pages, that was not accessed during the first period of time from the first memory to the second memory.
    Type: Application
    Filed: January 26, 2023
    Publication date: August 1, 2024
    Inventors: Pratap SUBRAHMANYAM, Venkata Subhash Reddy PEDDAMALLU, Isam Wadih AKKAWI, Andreas Georg NOWATZYK, Rajesh VENKATASUBRAMANIAN, Yijiang YUAN, Adarsh Seethanadi NAYAK, Nishchay DUA, Sreekanth SETTY
  • Publication number: 20240256439
    Abstract: Techniques for implementing a hardware-based cache controller in, e.g., a tiered memory computer system are provided. In one set of embodiments, the cache controller can flexibly operate in a number of different modes that aid the OS/hypervisor of the computer system in managing and optimizing its use of the system's memory tiers. In another set of embodiments, the cache controller can implement a hardware architecture that enables it to significantly reduce the probability of tag collisions, decouple cache capacity management from cache lookup and allocation, and handle multiple concurrent cache transactions.
    Type: Application
    Filed: January 26, 2023
    Publication date: August 1, 2024
    Inventors: Andreas Georg Nowatzyk, Pratap Subrahmanyam, Isam Wadih Akkawi, Adarsh Seethanadi Nayak, Nishchay Dua
  • Patent number: 12052093
    Abstract: Described herein are systems, methods, and software to manage time calibration associated with an oscillator of a computing system. In one example, a computing system monitors clock cycles for an oscillator on the computing system, receives timing messages from a server, and calculates the frequency of the oscillator at intervals based on the monitored clock cycles and timing messages. The computing system further identifies a temperature from a temperature sensor at each of the intervals and generates a function to demonstrate frequency of the oscillator versus temperatures from the temperature sensor based on the identified temperatures and frequencies at the intervals.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: July 30, 2024
    Assignee: VMware LLC
    Inventors: Ali Najafi, Michael Wei, Andreas Georg Nowatzyk, Amy Tai
  • Publication number: 20240220773
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.
    Type: Application
    Filed: December 4, 2023
    Publication date: July 4, 2024
    Inventors: Andreas Georg Nowatzyk, Olivier Temam
  • Patent number: 11948060
    Abstract: A three dimensional neural network accelerator that includes a first neural network accelerator tile that includes a first transmission coil, and a second neural network accelerator tile that includes a second transmission coil, wherein the first neural network accelerator tile is adjacent to and aligned vertically with the second neural network accelerator tile, and wherein the first transmission coil is configured to wirelessly communicate with the second transmission coil via inductive coupling.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: April 2, 2024
    Assignee: GOOGLE LLC
    Inventors: Andreas Georg Nowatzyk, Olivier Temam, Ravi Narayanaswami, Uday Kumar Dasari
  • Publication number: 20240028243
    Abstract: In one set of embodiments, a hardware module of a computer system can receive a stream of addresses corresponding to memory units being accessed by a central processing unit (CPU) of the computer system. The hardware module can further generate a frequency estimate for each address in the stream of addresses, the frequency estimate being indicative of a number of times a memory unit identified by the address has been accessed by the CPU, and can determine, based on the generated frequency estimates, a set of n most frequently accessed memory units.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Inventors: Andreas Georg Nowatzyk, Isam Wadih Akkawi, Pratap Subrahmanyam, Adarsh Seethanadi Nayak, Nishchay Dua
  • Patent number: 11868644
    Abstract: In one set of embodiments, a hardware module of a computer system can receive a stream of addresses corresponding to memory units being accessed by a central processing unit (CPU) of the computer system. The hardware module can further generate a frequency estimate for each address in the stream of addresses, the frequency estimate being indicative of a number of times a memory unit identified by the address has been accessed by the CPU, and can determine, based on the generated frequency estimates, a set of n most frequently accessed memory units.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: January 9, 2024
    Assignee: VMWARE, INC.
    Inventors: Andreas Georg Nowatzyk, Isam Wadih Akkawi, Pratap Subrahmanyam, Adarsh Seethanadi Nayak, Nishchay Dua
  • Patent number: 11836598
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: December 5, 2023
    Assignee: Google LLC
    Inventors: Andreas Georg Nowatzyk, Olivier Temam
  • Publication number: 20230089659
    Abstract: Described herein are systems, methods, and software to manage time calibration associated with an oscillator of a computing system. In one example, a computing system monitors clock cycles for an oscillator on the computing system, receives timing messages from a server, and calculates the frequency of the oscillator at intervals based on the monitored clock cycles and timing messages. The computing system further identifies a temperature from a temperature sensor at each of the intervals and generates a function to demonstrate frequency of the oscillator versus temperatures from the temperature sensor based on the identified temperatures and frequencies at the intervals.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 23, 2023
    Inventors: Ali Najafi, Michael Wei, Andreas Georg Nowatzyk, Amy Tai
  • Publication number: 20220147793
    Abstract: A three dimensional neural network accelerator that includes a first neural network accelerator tile that includes a first transmission coil, and a second neural network accelerator tile that includes a second transmission coil, wherein the first neural network accelerator tile is adjacent to and aligned vertically with the second neural network accelerator tile, and wherein the first transmission coil is configured to wirelessly communicate with the second transmission coil via inductive coupling.
    Type: Application
    Filed: January 7, 2022
    Publication date: May 12, 2022
    Inventors: Andreas Georg Nowatzyk, Olivier Temam, Ravi Narayanaswami, Uday Kumar Dasari
  • Publication number: 20210216853
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 15, 2021
    Inventors: Andreas Georg Nowatzyk, Olivier Temam
  • Patent number: 10963780
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: March 30, 2021
    Assignee: Google LLC
    Inventors: Andreas Georg Nowatzyk, Olivier Temam
  • Publication number: 20190065937
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.
    Type: Application
    Filed: August 24, 2017
    Publication date: February 28, 2019
    Inventors: Andreas Georg Nowatzyk, Olivier Temam
  • Publication number: 20180365553
    Abstract: A three dimensional neural network accelerator that includes a first neural network accelerator tile that includes a first transmission coil, and a second neural network accelerator tile that includes a second transmission coil, wherein the first neural network accelerator tile is adjacent to and aligned vertically with the second neural network accelerator tile, and wherein the first transmission coil is configured to wirelessly communicate with the second transmission coil via inductive coupling.
    Type: Application
    Filed: March 21, 2018
    Publication date: December 20, 2018
    Inventors: Andreas Georg Nowatzyk, Olivier Temam, Ravi Narayanaswami, Uday Kumar Dasari
  • Patent number: 9928460
    Abstract: A three dimensional neural network accelerator that includes a first neural network accelerator tile that includes a first transmission coil, and a second neural network accelerator tile that includes a second transmission coil, wherein the first neural network accelerator tile is adjacent to and aligned vertically with the second neural network accelerator tile, and wherein the first transmission coil is configured to wirelessly communicate with the second transmission coil via inductive coupling.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 27, 2018
    Assignee: Google LLC
    Inventors: Andreas Georg Nowatzyk, Olivier Temam, Ravi Narayanaswami, Uday Kumar Dasari
  • Patent number: 9514316
    Abstract: An optical security device can be used to view sensitive information provided in an obscured format via a potentially untrusted and/or compromised computer. The techniques described herein enable use of untrusted computers for access to sensitive information. The optical security device employs one or more forms of visual cryptography such as spatial cryptography and/or temporal cryptography in some instances via a programmable mask and/or a programmable color filter to reveal sensitive information that is provided in an obscured form by a potentially untrusted computer.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: December 6, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Ramakrishna Rao Kotla, Andreas Georg Nowatzyk
  • Patent number: 9418215
    Abstract: An optical security device can be used to view sensitive information provided in an obscured format via a potentially untrusted and/or compromised computer. The techniques described herein enable use of untrusted computers for access to sensitive information. The optical security device employs one or more forms of visual cryptography such as spatial cryptography and/or temporal cryptography in some instances via a programmable mask and/or a programmable color filter to reveal sensitive information that is provided in an obscured form by a potentially untrusted computer.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: August 16, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ramakrishna Kotla, Andreas Georg Nowatzyk