Patents by Inventor Andreas Graf von Schwerin

Andreas Graf von Schwerin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for reading nonvolatile semiconductor memory configurations
    Patent number: 6407945
    Abstract: A method for reading non-volatile semiconductor memory configurations includes determining a high threshold voltage and a low threshold voltage based on a charge state of a floating gate for a transistor, and applying a reverse bias between a bulk and a source of the transistor during reading.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: June 18, 2002
    Assignee: Infineon Technologies AG
    Inventors: Andreas Graf von Schwerin, Oskar Kowarik, Franz Schuler
  • Method for reading nonvolatile semiconductor memory configurations
    Publication number: 20020018366
    Abstract: A method for reading non-volatile semiconductor memory configurations includes determining a high threshold voltage and a low threshold voltage based on a charge state of a floating gate for a transistor, and applying a reverse bias between a bulk and a source of the transistor during reading.
    Type: Application
    Filed: March 13, 2001
    Publication date: February 14, 2002
    Inventors: Andreas Graf von Schwerin, Oskar Kowarik, Franz Schuler
  • Method of forming a non-volatile memory cell having a high coupling capacitance including forming an insulator mask, etching the mask, and forming a u-shaped floating gate
    Patent number: 6159796
    Abstract: In a non-volatile memory cell having a floating gate (EEPROM), it is necessary to achieve a large coupling capacitance between the floating gate and a control gate in which the gates take up as little space as possible. To that end, it is provided that a dielectric between the floating gate and the control gate runs, in portions, approximately perpendicularly to the surface of a semiconductor substrate, for example, with the control gate configured within a U-shaped or pot-shaped floating gate.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: December 12, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventors: Guido Wolfgang Dietz, Andreas Graf Von Schwerin