Abstract: A matrix of liquid crystal pixels (160) is provided. A digital-to-analog converter (DAC) (150) is coupled to the matrix and produces an output voltage that can be applied to one or more pixels in the matrix. The DAC (150) receives a multi-bit digital input and generates its output voltage to correspond to the digital input. The conversion function of the DAC is adapted to have a higher resolution within a voltage range in which most grayshade changes of the LCD occur.

Abstract: A matrix of liquid crystal pixels (160) is provided. A digital-to-analog converter (DAC) (150) is coupled to the matrix and produces an output voltage that can be applied to one or more pixels in the matrix. The DAC (150) receives a multi-bit digital input and generates its output voltage to correspond to the digital input. The conversion function of the DAC is adapted to have a higher resolution within a voltage range in which most grayshade changes of the LCD occur.

Abstract: A method and apparatus for providing a program counter value within a central processing unit is described. A program counter value comprises n bits and has to be increased by one of a plurality of different fixed increment values. Therefore, an upper partial content of the current program counter value and its value incremented by 1 is provided. Also, a plurality of lower partial contents of the current program counter value incremented by one of the plurality of fixed increment values, respectively are provided, whereby a carry bit is provided. One of the plurality of incremented lower partial contents is selected depending on said respective carry bit. Upper and lower contents are then combined to form a plurality of new program counter values. Upon receiving of control information to select a final increment value one of said new program counter values will be selected.

Abstract: A circuit configuration for synchronizing pulse-shaped signals includes a clock-controlled flip-flop having a data input for receiving a pulse-shaped signal to be synchronized, a data output for supplying a synchronized signal, and a clock input. A test circuit has an input connected to the data input of the clock-controlled flip-flop for receiving the pulse-shaped signal to be synchronized, another input for receiving at least one clock signal, and an output connected to the clock input of the clock-controlled flip-flop. The test circuit generates an output signal at the output of the test circuit to be supplied to the clock input of the clock-controlled flip-flop being either equal to or phase-offset relative to the at least one clock signal supplied to the other input of the test circuit. The test circuit ascertains a phase difference between an edge of the pulse-shaped signal to be weighted and a weighting edge of the output signal of the test circuit.