Abstract: A computer system improves a production yield of a semiconductor chip described by design data. The computer system includes a synthesis controller in signal communication with a yield optimization controller. The synthesis controller generates design data representing a design implementation of the semiconductor chip. The yield optimization controller extracts timing information from the design data. The timing information describes a slack related to a timing path within the semiconductor chip. The yield optimization controller further identifies one or more one yield improvable cells described by the design data, and determines from the design data an adverse impact of yield improvement on the slack. Based on the timing information and the determined adverse impact, the yield optimization controller calculates a subset of the yield improvable cell, and modifies the subset of the yield improvable cell so that the production yield is improved.

Abstract: Embodiments are disclosed for routing a cell of a semiconductor chip, the cell being represented by a matrix, encoding first tracks of the cell as columns of the matrix and second tracks of the cell as rows of the matrix, respectively. The method includes performing a sweep operation on the matrix, the sweep operation including generating an index structure indexed by columns of the matrix, the index structure including information on candidate cut shapes that can be placed in a particular column of the matrix. Additionally, the method includes recursively placing cut shapes into the cell based on the index structure, one recursion of the placing including finding a possible cut shape and recursively placing the remaining cut shapes.

Abstract: An integrated circuit is provided. The integrated circuit includes a plurality of skitter circuits and a multiplexer that provides the waveform to the plurality of skitter circuits. The plurality of skitter circuits includes at least a first skitter circuit and a second skitter circuit. The first and second skitter circuits are arranged in parallel with respect to an output of the multiplexer. The first skitter circuit can include a first data path and a plurality of first inverters on that first data path. Further, the second skitter circuit can include a second data path, a plurality of second inverters on the second data path, and a delay element connected in series with an input of an initial inverter of the plurality of the second inverters on the second data path.

Abstract: A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

Abstract: According to one or more embodiments of the present invention, a computer-implemented method includes determining, for a first sector from multiple sectors of a clock mesh of a semiconductor circuit, a set of mesh wires. The method further includes generating tapping point candidates, selecting a first combination of tapping points, and performing an analog electrical simulation of a clock signal. The simulation includes feeding the clock signal into the clock mesh via the first combination of tapping points via a clock signal transmitter, and measuring delays for the clock signal to reach a set of measuring nodes. The maximum delay from the measured delays is selected, and, in response to the maximum delay being less than a previous delay value, the first combination of tapping points is used to connect sector buffers from the first sector to the clock mesh.

Abstract: Aspects of the present disclosure relate to adaptive mesh wiring. A clock signal is provided to a clock mesh area, wherein the clock mesh area includes a plurality of wires configured in a grid. A pair of loads with impermissible skew within the clock mesh area is identified based on a threshold value. A mesh network area partition enclosing the pair of loads with impermissible skew is determined. Modifications are then made to the mesh network area partition to attempt to reduce skew. In some embodiments, a wire width of a portion of wires included in the mesh network area partition is increased. In some embodiments, a wire is added in between two wires present in the mesh network area partition.

Abstract: Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.

Abstract: Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.

Abstract: A duty cycle correction device may be provided for correcting a duty cycle of an input signal. The device includes a first duty cycle correction circuit. The first duty cycle correction circuit receives the input signal. The first duty cycle correction circuit generates a first intermediate signal. The device includes a first programmable delay circuit. The first programmable delay circuit is controlled by a first delay control signal. The first programmable delay circuit receives the first intermediate signal. The first programmable delay circuit generates an output signal. The device includes a second duty cycle correction circuit. The second duty cycle correction circuit receives the input signal. The second duty cycle correction circuit generates a second intermediate signal. The device includes a second programmable delay circuit. The second programmable delay circuit generates a reference signal. The device includes a skew control arrangement operable for generating the first delay control signal.

Abstract: The disclosure relates to a skew control circuit for controlling the skew between at least three clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals. The skew control circuit comprises multiple programmable delay elements arranged within a signal flow before the respective clock domain, a skew detector arrangement operable for detecting skews between at least two pairs of the clock signals, and a control circuit operable for adjusting delays caused by the programmable delay elements. The control circuit is operable for carrying out a de-skewing operation. The de-skewing operation comprises determining an order of occurrence of edges of the signals, selecting one of the programmable delay elements based on the determined order, and adjusting the delay caused by the selected programmable delay element.

Abstract: The disclosure relates to a skew control circuit for controlling the skew between at least three clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals. The skew control circuit comprises multiple programmable delay elements arranged within a signal flow before the respective clock domain, a skew detector arrangement operable for detecting skews between at least two pairs of the clock signals, and a control circuit operable for adjusting delays caused by the programmable delay elements. The control circuit is operable for carrying out a de-skewing operation. The de-skewing operation comprises determining an order of occurrence of edges of the signals, selecting one of the programmable delay elements based on the determined order, and adjusting the delay caused by the selected programmable delay element.

Abstract: In an approach for generating a file, a computer generates a modified layout for an integrated circuit. The computer receives a draft layout for an integrated circuit. The computer identifies a resonator, wherein the resonator comprises a capacitor connected to ground and an inductor connected to a clock grid. The computer creates alternative resonator wiring of the received draft layout associated with the identified resonator. The computer generates a modified draft layout based on the created alternative resonator wiring for the integrated circuit. The computer causes manufacture of an integrated circuit based on the generated modified draft layout.

Abstract: In an approach for generating a file, a computer generates a modified layout for an integrated circuit. The computer receives a draft layout for an integrated circuit. The computer identifies a resonator, wherein the resonator comprises a capacitor connected to ground and an inductor connected to a clock grid. The computer creates alternative resonator wiring of the received draft layout associated with the identified resonator. The computer generates a modified draft layout based on the created alternative resonator wiring for the integrated circuit.

Abstract: In an approach for generating a file, a computer generates a modified layout for an integrated circuit. The computer receives a draft layout for an integrated circuit. The computer identifies a resonator, wherein the resonator comprises a capacitor connected to ground and an inductor connected to a clock grid. The computer creates alternative resonator wiring of the received draft layout associated with the identified resonator. The computer generates a modified draft layout based on the created alternative resonator wiring for the integrated circuit.