Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: Clocks of two semiconductor circuit are set to a common clock source when both the first and second semiconductor circuits are in a slow clock speed at which an input/output (IO) at an interface between the first and second semiconductor circuit is capable of operating. Division counters of the two clocks are synchronized at the slow clock speed. The two semiconductor circuits are switched to a fast clock speed that is a multiple of the slow speed, wherein the IO is not capable of operating at the fast clock speed. Pulses from a division counter of the first circuit are sent to a spare division counter of the second circuit, and then a primary division counter of the second counter is aligned to this spare division counter to keep the two circuits synchronized at the fast clock speed.

Abstract: A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: Clocks of two semiconductor circuit are set to a common clock source when both the first and second semiconductor circuits are in a slow clock speed at which an input/output (TO) at an interface between the first and second semiconductor circuit is capable of operating. Division counters of the two clocks are synchronized at the slow clock speed. The two semiconductor circuits are switched to a fast clock speed that is a multiple of the slow speed, wherein the IO is not capable of operating at the fast clock speed. Pulses from a division counter of the first circuit are sent to a spare division counter of the second circuit, and then a primary division counter of the second counter is aligned to this spare division counter to keep the two circuits synchronized at the fast clock speed.

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: Measuring a control system response time of a second clock tree is provided, comprising measuring a skew between the second clock signal and the first clock signal and storing the skew, initiating a delay change of a delay induced by the programmable delay line and starting a time measurement. At least one iteration is performed of measuring the skew between the second clock signal and the first clock signal and comparing the measured skew with the stored skew. Based on the result of the comparison, stopping after a current iteration and stopping the time measurement. A result of the time measurement is the control system response time.

Abstract: A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

Abstract: A skew sensor for detecting skew between two input signals is provided. The skew sensor includes at least two skew detectors. The first skew detector receives either a first clock signal or a second clock signal as a first input signal, and the other one of the first clock signal and the second clock signal delayed by a first delay difference induced by one or more delay elements as a second input signal. The second skew detector receives either the first clock signal or the second clock signal as the first input signal, and the other one of the first clock signal and the second clock signal optionally delayed by a second delay difference induced by one more delay elements, wherein the second delay difference is different from the first delay difference, as the second input signal. Skew is measured between the first clock signal and the second clock signal.

Abstract: Embodiments are disclosed for routing a cell of a semiconductor chip, the cell being represented by a matrix, encoding first tracks of the cell as columns of the matrix and second tracks of the cell as rows of the matrix, respectively. The method includes performing a sweep operation on the matrix, the sweep operation including generating an index structure indexed by columns of the matrix, the index structure including information on candidate cut shapes that can be placed in a particular column of the matrix. Additionally, the method includes recursively placing cut shapes into the cell based on the index structure, one recursion of the placing including finding a possible cut shape and recursively placing the remaining cut shapes.

Abstract: A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

Abstract: A computer system improves a production yield of a semiconductor chip described by design data. The computer system includes a synthesis controller in signal communication with a yield optimization controller. The synthesis controller generates design data representing a design implementation of the semiconductor chip. The yield optimization controller extracts timing information from the design data. The timing information describes a slack related to a timing path within the semiconductor chip. The yield optimization controller further identifies one or more one yield improvable cells described by the design data, and determines from the design data an adverse impact of yield improvement on the slack. Based on the timing information and the determined adverse impact, the yield optimization controller calculates a subset of the yield improvable cell, and modifies the subset of the yield improvable cell so that the production yield is improved.

Abstract: An integrated circuit is provided. The integrated circuit includes a plurality of skitter circuits and a multiplexer that provides the waveform to the plurality of skitter circuits. The plurality of skitter circuits includes at least a first skitter circuit and a second skitter circuit. The first and second skitter circuits are arranged in parallel with respect to an output of the multiplexer. The first skitter circuit can include a first data path and a plurality of first inverters on that first data path. Further, the second skitter circuit can include a second data path, a plurality of second inverters on the second data path, and a delay element connected in series with an input of an initial inverter of the plurality of the second inverters on the second data path.

Abstract: A skew sensor for detecting skew between two input signals is provided. The skew sensor includes at least two skew detectors. The first skew detector receives either a first clock signal or a second clock signal as a first input signal, and the other one of the first clock signal and the second clock signal delayed by a first delay difference induced by one or more delay elements as a second input signal. The second skew detector receives either the first clock signal or the second clock signal as the first input signal, and the other one of the first clock signal and the second clock signal optionally delayed by a second delay difference induced by one more delay elements, wherein the second delay difference is different from the first delay difference, as the second input signal. Skew is measured between the first clock signal and the second clock signal.

Abstract: Measuring a control system response time of a second clock tree is provided, comprising measuring a skew between the second clock signal and the first clock signal and storing the skew, initiating a delay change of a delay induced by the programmable delay line and starting a time measurement. At least one iteration is performed of measuring the skew between the second clock signal and the first clock signal and comparing the measured skew with the stored skew. Based on the result of the comparison, stopping after a current iteration and stopping the time measurement. A result of the time measurement is the control system response time.

Abstract: A method for cycle accurate deskewing a second clock signal with respect to a first clock signal is provided. The first clock signal has been propagated from a first clock source through a first clock tree. The second clock signal has been propagated from the first clock source through a second clock tree. The second clock tree comprises a programmable delay line for inducing a delay. The method comprises determining a first clock tree latency of the first clock tree, determining a second clock tree latency of the second clock tree, setting a cycle time of the first clock source to a measuring cycle time depending on the first clock tree latency and/or the second clock tree latency, adjusting a skew between the second clock signal and the first clock signal, setting the cycle time of the first clock source to an operating cycle time.

Abstract: A method for cycle accurate deskewing a second clock signal with respect to a first clock signal is provided. The first clock signal has been propagated from a first clock source through a first clock tree. The second clock signal has been propagated from the first clock source through a second clock tree. The second clock tree comprises a programmable delay line for inducing a delay. The method comprises determining a first clock tree latency of the first clock tree, determining a second clock tree latency of the second clock tree, setting a cycle time of the first clock source to a measuring cycle time depending on the first clock tree latency and/or the second clock tree latency, adjusting a skew between the second clock signal and the first clock signal, setting the cycle time of the first clock source to an operating cycle time.

Abstract: A computer system improves a production yield of a semiconductor chip described by design data. The computer system includes a synthesis controller in signal communication with a yield optimization controller. The synthesis controller generates design data representing a design implementation of the semiconductor chip. The yield optimization controller extracts timing information from the design data. The timing information describes a slack related to a timing path within the semiconductor chip. The yield optimization controller further identifies one or more one yield improvable cells described by the design data, and determines from the design data an adverse impact of yield improvement on the slack. Based on the timing information and the determined adverse impact, the yield optimization controller calculates a subset of the yield improvable cell, and modifies the subset of the yield improvable cell so that the production yield is improved.

Abstract: A method for adjusting a skew between a second clock signal and a first clock signal is provided. The second clock signal has been propagated from a first clock source through a second clock tree. The second clock tree comprises a programmable delay line that induces a delay. The method comprises at least one iteration of: measuring a skew between the second clock signal and the first clock signal, comparing an absolute difference of the measured skew and a sum of delay changes initiated in a time window preceding the measurement with a target skew, and initiating a delay change of the delay induced by the programmable delay line in the second clock tree depending on a result of the comparison.