Abstract: A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.

Abstract: In transistors with sub-micron channels, short-channel effects, such as a lowering of the threshold voltage, are usually suppressed by means of a halo (or pocket) implant in the source/drain regions, which operation is performed jointly with the LDD implantation. The halo implant, however, decreases the analog performance of transistors. To combine suppression of short-channel effects with a high analog performance, it is proposed to provide only transistors T1, which are not intended for analog functions with the halo implant (16), and to mask the analog transistors T2 with a mask (15) against the halo implant. To avoid short-channel effects in T2, this transistor is provided with a channel whose length is larger than that of transistor T1.

Abstract: In a method of manufacturing a semiconductor device comprising a transistor having a gate insulated from a channel region at a surface of a semiconductor body by a gate dielectric, an active region 4 of a first conductivity type is defined at the surface 2 of the semiconductor body 1, and a patterned layer is applied consisting of refractory material, which patterned layer defines the area of the planned gate to be provided at a later stage of the process and acts as a mask during the formation of a source zone 11 and a drain zone 12 of a second conductivity type in the semiconductor body 1. In a next step, a dielectric layer 14 is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer 14 is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess 15 in the dielectric layer 14 at the area of the planned gate.

Abstract: In a method of manufacturing a semiconductor device comprising a non-volatile memory element, an active region 4 of a first conductivity type is defined at a surface 2 of a semiconductor body 1, and a patterned layer is applied, which patterned layer acts as a mask during the formation of a source zone 11 and a drain zone 12 of a second conductivity type in the semiconductor body 1. Then, a dielectric layer 14 is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer 14 is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess in the dielectric layer 14.

Abstract: Amorphous or polycrystalline silicon layers are sometimes used in the metallization steps of IC processes, for example as antireflex coatings or as etching stopper layers for etching back of tungsten. A problem is that such a layer cannot be provided by CVD or LPCVD on account of the high deposition temperature which is not compatible with standard Al metallizations. Other deposition techniques, such as sputtering or plasma CVD, often lead to a lesser material quality, a longer processing time per wafer, or a worse step covering. According to the invention, the layer is provided by CVD or LPCVD at a temperature below 500° C. under the addition of Ge. The GexSi1−x layer (8) thus obtained is found to have good properties as regards step covering, optical aspects, electrical aspects, and etching aspects, and is compatible with any Al metallization (6) already present.

Abstract: In a method of manufacturing a semiconductor device comprising a field-effect transistor and a non-volatile memory element at a surface of a semiconductor body, a first and a second active region of a first conductivity type are defined at the surface of the semiconductor body for the transistor and the memory element, respectively. The surface of the semiconductor body is subsequently coated with a first insulating layer providing a sacrificial gate dielectric of the transistor and a floating gate dielectric of the memory element, which first insulating layer is then covered by a silicon-containing layer providing a sacrificial gate of the transistor and a floating gate of the memory element. After formation of the sacrificial gate and the floating gate, the transistor and the memory element are provided with source and drain zones of a second conductivity type.

Abstract: In the known replacement gate process, the relatively high-ohmic poly gate is replaced by a low-ohmic metal gate by depositing a thick oxide layer and subsequently planarizing this layer by CMP until the gate is reached, which gate can be selectively removed and replaced by a metal gate. The process is simplified considerably by providing the gate structure as a stack of a dummy poly gate (4) and a nitride layer (5) on top of the poly gate. When, during the CMP, the nitride layer is reached, the CMP is stopped, thereby precluding an attack on the poly. The nitride and the poly are selectively removed relative to the oxide layer (10).

Abstract: Very high resistance values may be necessary in integrated circuits, for example in the gigaohm range, for example for realizing RC times of 1 ms to 1 s. Such resistance values cannot or substantially not be realized by known methods in standard i.c. processes because of the too large space occupation. In addition, known embodiments are usually strongly dependent on the temperature. According to the invention, therefore, two zener diodes (10, 4; 11, 4) connected back-to-back are used as the resistor. The current through each zener diode is mainly determined by band--band tunneling when the voltage is not too high, for example up to approximately 0.2 V. This current has a value such that resistors in the giga range can be readily realized on a small surface area. Since the current is mainly determined by intrinsic material properties of silicon, the temperature dependence is very small. The resistor may furthermore be manufactured in any standard CMOS process or bipolar process.

Abstract: A method of manufacturing a semiconductor device includes forming field oxide regions (17) in a surface (1) of a silicon body (2) through oxidation, which body is provided with an oxidation mask (15) formed in a layered structure provided on the surface with a lower layer (4) of silicon oxide, an intermediate layer (5) of polycrystalline silicon and an upper layer (6) of a material including silicon nitride in which windows (8) are etched into the upper layer. The intermediate layer is etched away inside the windows and below an edge (10) of the windows, a cavity (11) is formed below the edge, and a material including silicon nitride is provided in the cavity. The material including silicon nitride is provided in the cavity while the surface of the silicon body situated inside the windows is still covered by a layer of silicon oxide, preferably with the lower layer of the layered structure.