Abstract: A semiconductor package includes a die pad comprising a die attach surface, a first lead extending away from the die pad, one or more semiconductor dies mounted on the die attach surface, the one or more semiconductor dies comprising first and second bond pads that each face away from the die attach surface, and a distribution element that provides a first transmission path for a first electrical signal between the first lead and the first bond pad of the one or more semiconductor dies and a second transmission path for the first electrical signal between the first lead and the second bond pad of the one or more semiconductor dies. The distribution element comprises at least one integrally formed circuit element that creates a difference in transmission characteristics between the first and second transmission paths.

Abstract: A silicon carbide semiconductor device includes a first load electrode disposed on a first surface of a silicon carbide semiconductor body, a first doped region disposed in the silicon carbide semiconductor body and electrically connected to the first load electrode, and an insulated gate field effect transistor electrically connected in series with the first doped region, the insulated gate field effect transistor including a source region and a body region, the body region being electrically connected to the first load electrode, wherein a geometry and dopant concentration of the first doped region is such that a resistance of the first doped region increases by at least a factor of two as load current in the insulated gate field effect transistor rises.

Abstract: A semiconductor device is provided. In an embodiment, the semiconductor device comprises a control region, a first power region, a second power region, an isolation region and/or a short circuit structure. The control region comprises a control terminal. The first power region comprises a first power terminal. The second power region comprises a second power terminal. The isolation region is between the control region and the first power region. The short circuit structure extends from the first power region, through the isolation region, to the control region. The short circuit structure is configured to form a low-resistive connection between the control region and the first power region during a failure state of the semiconductor device.

Abstract: A semiconductor package includes a die pad comprising a die attach surface, a first lead extending away from the die pad, one or more semiconductor dies mounted on the die attach surface, the one or more semiconductor dies comprising first and second bond pads that each face away from the die attach surface, and a distribution element that provides a first transmission path for a first electrical signal between the first lead and the first bond pad of the one or more semiconductor dies and a second transmission path for the first electrical signal between the first lead and the second bond pad of the one or more semiconductor dies. The distribution element comprises at least one integrally formed circuit element that creates a difference in transmission characteristics between the first and second transmission paths.

Abstract: A silicon carbide semiconductor device includes a first load electrode disposed on a first surface of a silicon carbide semiconductor body, a first doped region disposed in the silicon carbide semiconductor body and electrically connected to the first load electrode, and an insulated gate field effect transistor electrically connected in series with the first doped region, the insulated gate field effect transistor including a source region and a body region, the body region being electrically connected to the first load electrode, wherein a geometry and dopant concentration of the first doped region is such that a resistance of the first doped region increases by at least a factor of two as load current in the insulated gate field effect transistor rises.

Abstract: A SiC semiconductor device includes a first load electrode, a normally-on junction field effect transistor, and an insulated gate field effect transistor. The normally-on junction field effect transistor includes a channel region electrically connected to the first load electrode. The insulated gate field effect transistor and the normally-on junction field effect transistor are electrically connected in series. The insulated gate field effect transistor includes a source region and a body region. The source region is electrically connected to a channel region of the normally-on junction field effect transistor. The body is electrically connected to the first load electrode.

Abstract: A semiconductor device is provided. In an embodiment, the semiconductor device comprises a control region, a first power region, a second power region, an isolation region and/or a short circuit structure. The control region comprises a control terminal. The first power region comprises a first power terminal. The second power region comprises a second power terminal. The isolation region is between the control region and the first power region. The short circuit structure extends from the first power region, through the isolation region, to the control region. The short circuit structure is configured to form a low-resistive connection between the control region and the first power region during a failure state of the semiconductor device.

Abstract: A SiC semiconductor device includes a first load electrode, a normally-on junction field effect transistor, and an insulated gate field effect transistor. The normally-on junction field effect transistor includes a channel region electrically connected to the first load electrode. The insulated gate field effect transistor and the normally-on junction field effect transistor are electrically connected in series. The insulated gate field effect transistor includes a source region and a body region. The source region is electrically connected to a channel region of the normally-on junction field effect transistor. The body is electrically connected to the first load electrode.

Abstract: In a semiconductor switch with a monolithically integrated field effect transistor, the source or emitter region of the field effect transistor is connected via a semiconductor region and an n-doped contact region to a first electrical terminal. In the semiconductor region, a semiconductor structure with n-doped channels is formed between the n-doped contact region and the source or emitter region of the field effect transistor; the n-doped channels electrically connect the n-doped contact region with the source or emitter region of the field effect transistor and run between p-doped regions that are connected to the n-doped contact region. The semiconductor switch is suitable as a self-switching load disconnector and has low losses in the switched-on state.

Abstract: In a semiconductor switch with a monolithically integrated field effect transistor, the source or emitter region of the field effect transistor is connected via a semiconductor region and an n-doped contact region to a first electrical terminal. In the semiconductor region, a semiconductor structure with n-doped channels is formed between the n-doped contact region and the source or emitter region of the field effect transistor; the n-doped channels electrically connect the n-doped contact region with the source or emitter region of the field effect transistor and run between p-doped regions that are connected to the n-doped contact region. The semiconductor switch is suitable as a self-switching load disconnector and has low losses in the switched-on state.

Abstract: The invention disclosure describes a manufacturing method for realizing so-called JBS areas for a unipolar power diode on the basis of diamond. In this special method, an n-doped layer is applied to the typically p-doped drift region, e.g. by means of epitaxial layer growth. The applied n-doped layer is then removed again in defined areas. A photolithographic mask may be applied and the n-doped layer is removed by dry or wet chemical etching. Having structured the JBS areas, the Schottky metal is applied to the entire surface. The resulting JBS structure shields an electric field generated by an applied reverse voltage from the Schottky transition. The reverse voltage from which the Schottky transition is fully shielded can be adjusted by altering the distance between the JBS areas.

Abstract: The invention disclosure describes a manufacturing method for realizing so-called JBS areas for a unipolar power diode on the basis of diamond. In this special method, an n-doped layer is applied to the typically p-doped drift region, e.g. by means of epitaxial layer growth. The applied n-doped layer is then removed again in defined areas. A photolithographic mask may be applied and the n-doped layer is removed by dry or wet chemical etching. Having structured the JBS areas, the Schottky metal is applied to the entire surface. The resulting JBS structure shields an electric field generated by an applied reverse voltage from the Schottky transition. The reverse voltage from which the Schottky transition is fully shielded can be adjusted by altering the distance between the JBS areas.

Abstract: A monolithically integrated semiconductor switch, particularly a circuit breaker, has regenerative turn-off behavior. The semiconductor switch has two monolithically integrated field effect transistors, for example a p-JFET and a n-JFET. The source electrodes of both JFETs and the well region of the n-JFET are short circuited. In addition, the gate electrodes of both JFETs and the drain electrode of the p-JFET are short-circuited via the cathode. In contrast, the well region of the p-JFET is short-circuited to the anode. In this way, a monolithically integrated semiconductor switch is created which turns off automatically when a certain anode voltage level or a certain anode current level is exceeded. The threshold values for the anode voltage and the anode current can be set by appropriate dimensioning of the elements. In this way, it is possible to achieve blocking strengths of up to 200 kV with fast response behavior.

Abstract: A monolithically integrated semiconductor switch, particularly a circuit breaker, has regenerative turn-off behaviour. The semiconductor switch has two monolithically integrated field effect transistors, for example a p-JFET and a n-JFET. The source electrodes of both JFETs and the well region of the n-JFET are short circuited. In addition, the gate electrodes of both JFETs and the drain electrode of the p-JFET are short-circuited via the cathode. In contrast, the well region of the p-JFET is short-circuited to the anode. In this way, a monolithically integrated semiconductor switch is created which turns off automatically when a certain anode voltage level or a certain anode current level is exceeded. The threshold values for the anode voltage and the anode current can be set by appropriate dimensioning of the elements. In this way, it is possible to achieve blocking strengths of up to 200 kV with fast response behaviour.