Patents by Inventor Andreas Haghofer

Andreas Haghofer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200227518
    Abstract: A semiconductor device includes a plurality of first and second stripe-shaped cell trench structures formed in a semiconductor substrate and extending lengthwise in parallel with one another. Each stripe-shaped cell trench structure includes a buried electrode and an insulator layer between the buried electrode and the semiconductor substrate. A recess is formed in the insulator layer along a sidewall of one or more of the first stripe-shaped cell trench structures and vertically extends to a corresponding heavily doped contact zone. An electrically conductive material disposed in each recess contacts the corresponding buried electrode, a corresponding source zone and a corresponding heavily doped contact zone at the sidewall. Two or more of the first stripe-shaped cell trench structures are interposed between neighboring ones of the second stripe-shaped cell trench structures. Source zones alternate with portions of body zones in a lateral direction parallel to the stripe-shaped cell trench structures.
    Type: Application
    Filed: March 24, 2020
    Publication date: July 16, 2020
    Inventors: Johannes Georg Laven, Maria Cotorogea, Hans-Joachim Schulze, Haybat Itani, Erich Griebl, Andreas Haghofer
  • Patent number: 10629676
    Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: April 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Maria Cotorogea, Hans-Joachim Schulze, Haybat Itani, Erich Griebl, Andreas Haghofer
  • Publication number: 20180366541
    Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.
    Type: Application
    Filed: August 23, 2018
    Publication date: December 20, 2018
    Inventors: Johannes Georg Laven, Maria Cotorogea, Hans-Joachim Schulze, Haybat Itani, Erich Griebl, Andreas Haghofer
  • Patent number: 10128133
    Abstract: An etching tool that includes an interior chamber is provided. A plurality of type III-V semiconductor wafers is provided. A process cycle is performed for each one of the type III-V semiconductor wafers in the plurality. The process cycle includes performing a preliminary contamination control process. The process cycle further includes inserting one of the type III-V semiconductor wafers into the interior chamber. The process cycle further includes etching type III-V semiconductor material away from the type III-V semiconductor wafer that is present in the interior chamber. The process cycle further includes removing the type III-V semiconductor wafer that is present in the interior chamber. The preliminary contamination control process includes forming a carbon containing protective material that completely covers exposed surfaces of the interior chamber.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 13, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Haghofer, Clemens Ostermaier
  • Patent number: 9768273
    Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 19, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ravi Joshi, Johannes Baumgartl, Martin Poelzl, Matthias Kuenle, Juergen Steinbrenner, Andreas Haghofer, Christoph Gruber, Georg Ehrentraut
  • Publication number: 20170243969
    Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.
    Type: Application
    Filed: May 8, 2017
    Publication date: August 24, 2017
    Inventors: Johannes Georg Laven, Maria Cotorogea, Hans-Joachim Schulze, Haybat Itani, Erich Griebl, Andreas Haghofer
  • Patent number: 9666663
    Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: May 30, 2017
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Maria Cotorogea, Hans-Joachim Schulze, Haybat Itani, Erich Griebl, Andreas Haghofer
  • Publication number: 20170005091
    Abstract: A semiconductor device includes a semiconductor laminar structure arranged on a semiconductor substrate. The semiconductor laminar structure includes a first doping region of a field effect transistor structure and at least a part of a body region of the field effect transistor structure. The body region has a first conductivity type and the first doping region has a second conductivity type. The semiconductor device further includes an electrically conductive contact structure providing an electrical contact to the first doping region of the field effect transistor structure and to the body region of the field effect transistor structure at one or more sidewalls of the semiconductor laminar structure.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 5, 2017
    Inventors: Ravi Keshav Joshi, Johannes Baumgartl, Christoph Gruber, Andreas Haghofer, Martin Poelzl, Juergen Steinbrenner
  • Publication number: 20160308028
    Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.
    Type: Application
    Filed: June 20, 2016
    Publication date: October 20, 2016
    Inventors: Ravi Joshi, Johannes Baumgartl, Martin Poelzl, Matthias Kuenle, Juergen Steinbrenner, Andreas Haghofer, Christoph Gruber, Georg Ehrentraut
  • Patent number: 9379196
    Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: June 28, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ravi Joshi, Johannes Baumgartl, Martin Poelzl, Matthias Kuenle, Juergen Steinbrenner, Andreas Haghofer, Christoph Gruber, Georg Ehrentraut
  • Publication number: 20150221735
    Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.
    Type: Application
    Filed: February 6, 2014
    Publication date: August 6, 2015
    Inventors: Ravi Joshi, Johannes Baumgartl, Martin Poelzl, Matthias Kuenle, Juergen Steinbrenner, Andreas Haghofer, Christoph Gruber, Georg Ehrentraut
  • Publication number: 20150041962
    Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 12, 2015
    Inventors: Johannes Georg Laven, Maria Cotorogea, Hans-Joachim Schulze, Haybat Itani, Erich Griebl, Andreas Haghofer