Abstract: Provided is a resource manager. The resource manager may be a memory manager which is configured to determine a plurality of eviction rankings, wherein each of the plurality of eviction rankings assigns a position within the eviction ranking to each of a plurality of eviction candidates based on at least one eviction criterion. The memory manager may then select one of said eviction candidates by applying a voting algorithm to the plurality of eviction rankings and cause the selected eviction candidate to be evicted.

Abstract: A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.

Abstract: A method for dynamically programming Field Programmable Gate Arrays (FPGA in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising thecoprocessor and processor are provided as well.

Abstract: The invention is directed to methods, apparatus and systems for processing a data packet that has a destination address. In the event that in a routing table cache and in a routing table, there is no entry with a destination address prefix that is a prefix of the destination address, a default-route-prefix is determined in a default-route determination step.

Abstract: A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.

Abstract: Described is a method and system for processing data packets of a data stream in a communication system. The data packets are processed depending on a feature of the header of a data packet in a faster path or in a slower path. To avoid a disorder by the different processing paths, the fast processed data packets are stored in a memory. The stored fast processed data packets are output after all slowly processed data packets which before the processing were in order before the fast data packets have been put to the output. In this way, the processed data packets are in the same order as prior to the processing.

Abstract: A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collisions of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.

Abstract: A method and systems for dynamically distributing packet flows over multiple network processing means and recombining packet flows after processing while keeping packet order even for traffic wherein an individual flow exceeds the performance capabilities of a single network processing means is disclosed. After incoming packets have been analyzed to identify the flow the packets are parts of, the sequenced load balancer of the invention dynamically distributes packets to the connected independent network processors. A balance history is created per flow and updated each time a packet of the flow is received and/or transmitted. Each balance history memorizes, in time order, the identifier of network processor having handled packets of the flow and the associated number of processed packets. Processed packets are then transmitted back to a high-speed link or memorized to be transmitted back to the high-speed link later, depending upon the current status of the balance history.

Abstract: A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collision of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.

Abstract: A method (and apparatus) for determining, in a system including an m-bit time counter, whether an event-occurrence time lies after a predetermined timeout-value, includes reading out of a time-stamp memory a stored time-stamp value, determining the time-difference between the time-stamp value and the event-occurrence time, and determining whether the time-difference is larger than the predetermined timeout-value. The event-occurrence time is represented by a subset of the bits of the m-bit time counter, the subset being determined by a plurality of parameters including any two of a lower bit-position, an upper bit-position, and a subset width. The lower bit-position is dependent on the predetermined timeout-value.

Abstract: The present invention provides a method and system handling information exchange through networks 102 to 110 for interactive information exchange, especially for interactive Internet based game show. At least one server 120 and a plurality of client machines 130 to 146 are connected through the networks 102 to 110. First, the server 120 receives subscription messages from a subset of said client machines 130 to 146. By receiving the subscription messages from the client machines 130 to 146 the provider of the particular program knows which users want to participate in the program. In response, the server 120 composes a request message offering predetermined response options, whereby corresponding response messages are returned through said networks 102 to 110 in one or more packets. In parallel, packet forwarding rules are set up in said networks 102 to 110 specifying a particular treatment for said returned packets dependent on said predetermined response options.

Abstract: The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1.

Abstract: A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent a collisions of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.

Abstract: A method and systems for dynamically distributing packet flows over multiple network processing means and recombining packet flows after processing while keeping packet order even for traffic wherein an individual flow exceeds the performance capabilities of a single network processing means is disclosed. After incoming packets have been analyzed to identify the flow the packets are parts of, the sequenced load balancer of the invention dynamically distributes packets to the connected independent network processors. A balance history is created per flow and updated each time a packet of the flow is received and/or transmitted. Each balance history memorizes, in time order, the identifier of network processor having handled packets of the flow and the associated number of processed packets. Processed packets are then transmitted back to a high-speed link or memorized to be transmitted back to the high-speed link later, depending upon the current status of the balance history.

Abstract: Provides evaluation and management of system resources in a data processing system, particularly in a SoC device and for optimizing the operation of the system wherein the system having a plurality of components each operable to process dedicated tasks in the data processing system, wherein each of the components has its associated current resource usages depending on the currently processed task and/or its future resource usage depending on the tasks to be processed next, wherein the resource usage indicates the type of resources and the amount of resources used, wherein the processing of the task of at least one of the components can be modified to adapt the resource usage of this or other component. A method including: determining operating states; estimating current and future resource usage; if necessary adapting task processing according to a predefined scheme to reduce the-resource usage.

Abstract: A method for dynamically programming Field Programmable Gate Arrays (FPGA) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.

Abstract: A real-time load-balancing system for distributing a sequence of incoming data packets emanating from a high speed communication line to a plurality of processing means, each operating at a capacity that is lower than the capacity of the high speed communication line; the system according to the invention comprises: a parser capable of extracting a configurable set of classifier bits from the incoming packets for feeding into a compression means; the compression means is capable of reducing a bit pattern of length K to a bit pattern having a length L which is a fraction of K; a pipeline block for delaying incoming packets until a load balancing decision is found, and an inverse demultiplexer for receiving a port identifier output from said compression means as selector and for directing pipelined packets to the appropriate output port.

Abstract: The present invention provides a method and apparatus for altering the header having a layered structure of a frame in transit through a network node. Frame alteration commands issued by layer processing modules are assigned at relative positions with respect to the starting position of the layer. The relative positions with respect to each layer are further adjusted to adjusted relative positions in dependence on frame alteration commands previously assigned in the same layer. After translation of the adjusted relative positions to absolute positions, the frame alteration commands are executed sequentially by a frame alteration unit.

Abstract: The invention is directed to methods, apparatus and systems for processing a data packet that has a destination address. In the event that in a routing table cache and in a routing table, there is no entry with a destination address prefix that is a prefix of the destination address, a default-route-prefix is determined in a default-route determination step.

Abstract: Described is a method and system for processing data packets of a data stream in a communication system. The data packets are processed depending on a feature of the header of a data packet in a faster path or in a slower path. To avoid a disorder by the different processing paths, the fast processed data packets are stored in a memory. The stored fast processed data packets are output after all slowly processed data packets which before the processing were in order before the fast data packets have been put to the output. In this way, the processed data packets are in the same order as prior to the processing.