Abstract: The method comprises: the reverse transcription of the template RNA, the amplification and high-throughput sequencing of the cDNAs obtained in this way, the mapping of the sequenced cDNAs/reads to the reference genome using computerized alignment methods, a computerized evaluation of the mapping results with regard to the reverse transcription event pattern (the RT signature) at the nucleotide positions and feeding the digitalised data of the RT signatures into a computerized machine learning based classification system. Reverse transcription is carried out in parallel reaction batches with different reverse transcriptases and/or under different reaction conditions. The evaluation of the mapping results with regard to the RT signature is carried out using the events ‘arrest’ and/or ‘readthrough with mismatch’ and/or ‘readthrough with sequence gap(s)’. RT signature data obtained using the parallel reaction batches are fed into the classification system.

Abstract: Invention relates to a capacitive proximity switch with an electrical bridge circuit for detecting of an electrically conducting face (15) approaching or moving away, wherein the electrically conducting face (15) is part of a capacitor (for example C1) of the bridge circuit, wherein at least one capacitor (C1, C2, C3, C4) and possibly at least one resistor (R9, R10) are disposed in the bridge branches of the bridge circuit as further reactances, and wherein the bridge is subjected to an alternating voltage as a bridge feed voltage (ubr). The proximity switch includes a flat multilayer printed circuit board (10) having at least two electrically insulating layers (13, 14), wherein an electrically conducting intermediate layer (11) as a first face of a capacitor is disposed between the two electrically insulating layers (13, 14).

Abstract: The circuit arrangement and method is for measuring a difference in capacitance between a first capacitance (C.sub.1) and a second capacitance (C.sub.2). A hitherto necessary compensation of a plurality of parasitic effects has become unnecessary due to isolated measurement of an unwanted capacitance (C.sub.P) with which parasitic effects, to which the first capacitance (C.sub.1) and the second capacitance (C.sub.2) are subject, are modelled. When an evaluation logic (AL) realized in digital form is employed, only one counter unit wherein a binary value proportional to the respectively measured capacitance is counted need be provided. By cyclical measurement of the unwanted capacitance (C.sub.P), the first capacitance (C.sub.1), the second capacitance (C.sub.2) and, at the end, the unwanted capacitance (C.sub.P) are determined. The unwanted capacitance (C.sub.P) is compensated when the counter unit respectively counts backward when "counting" the unwanted capacitance (C.sub.P) but otherwise counts forward.

Abstract: In a circuit arrangement for determining differences in capacitance, two capacitors (1,2) are alternately connected to an integrator with differential amplifier (3) whose input current is positive (+I) when the first capacitor (1) is integrated or negative (-I) when the second capacitor (2) is integrated, whereby the switches (5,6,7) are synchronously switched. The differential amplifier keeps the voltages at the two capacitors the same. A clocked control device (4) controls the synchronous switching and separately measures and adds the respective charging and discharging times and, as warranted, measures and adds the output voltage of the integrator and controls the last charging cycle such that the voltage at the capacitors is subsequently equal to the initial voltage. The relative or absolute differences in capacitance are calculated from the identified sums and can be digitally output.