Patents by Inventor Andreas Hilliger
Andreas Hilliger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050013091Abstract: A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.Type: ApplicationFiled: July 18, 2003Publication date: January 20, 2005Inventors: Andreas Hilliger, Jingyu Lian, Nicolas Nagel, Rainer Bruchhaus, Stefan Gernhardt, Uwe Wellhausen, Bum-Ki Moon, Karl Hornik
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Patent number: 6839220Abstract: A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.Type: GrantFiled: July 18, 2003Date of Patent: January 4, 2005Assignee: Infineon Technologies AGInventors: Andreas Hilliger, Jingyu Lian, Nicolas Nagel, Rainer Bruchhaus, Stefan Gernhardt, Uwe Wellhausen, Bum-Ki Moon, Karl Hornik
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Publication number: 20040232457Abstract: An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel. The capacitor includes first and second subcapacitors, one stacked one on top of the other. Providing a capacitor with two,or more subcapacitors in a stack advantageously increases the capacitance of a capacitor without increasing surface area.Type: ApplicationFiled: December 30, 2002Publication date: November 25, 2004Inventors: Joerg Wohlfahrt, Rainer Bruchhaus, Andreas Hilliger
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Patent number: 6815234Abstract: A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the backside of the chip. The stress compensating layer produces a stress opposite of that produced by the IC. Thus the overall or effective stress on the substrate is reduced.Type: GrantFiled: December 31, 2002Date of Patent: November 9, 2004Assignee: Infineon Technologies AktiengesellschaftInventors: Uwe Wellhausen, Stefan Gernhardt, Rainer Bruchhaus, Andreás Hilliger, Jing Yu Lian, Nicolas Nagel
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Publication number: 20040206993Abstract: A ferrocapacitor device comprising a ferroelectric capacitor structure which includes a bottom electrode 5, a ferroelectric layer 7, and a top electrode 9, formed over a substructure 1. A first Al2O3 cover layer 15 is deposited over the structure by a physical vapour deposition process (such as sputtering), and a second Al2O3 cover layer 17 is deposited over the first Al2O3 cover layer 15 by atomic layer deposition. The first Al2O3 cover layer 15 protects the capacitor structure during the formation of the second Al2O3 cover layer 17, and the second Al2O3 cover layer 17 protects the capacitor structure during back end processes performed on the FeRAM device.Type: ApplicationFiled: April 17, 2003Publication date: October 21, 2004Applicants: Infineon Technologies AG, Kabushiki Kaisha ToshibaInventors: Karl Hornik, Haoren Zhuang, Bum Ki Moon, Andreas Hilliger, Katsuaki Natori
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Publication number: 20040201049Abstract: An electrode 1 of a ferrocapacitor formed by an etching process is treated by oxygen implantation to reduce the size of crystal domains 15 in side regions 11 of the electrode 1. Subsequently a cover layer 3 is deposited over the side wall of the electrode to protect the ferrocapacitor in subsequent process steps. Later in the fabrication process the ferrocapacitor is subject to heat treatments, but due to the reduced size of the crystal domains 15 the growth of the crystal domains in the side regions 11 of the electrode is more homogenous, and causes reduced stresses in the cover layer 3, leading to a reduced risk of the cover layer 3 failing to protect the ferrocapacitor.Type: ApplicationFiled: April 11, 2003Publication date: October 14, 2004Inventors: Stefan Gernhardt, Jingyu Lian, Rainer Bruchhaus, Andreas Hilliger, Nicolas Nagel, Uwe Wellhausen
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Patent number: 6800890Abstract: An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel. The capacitor includes first and second subcapacitors, one stacked one on top of the other. Providing a capacitor with two or more subcapacitors in a stack advantageously increases the capacitance of a capacitor without increasing surface area.Type: GrantFiled: December 30, 2002Date of Patent: October 5, 2004Assignee: Infineon Technologies AktiengesellschaftInventors: Joerg Wohlfahrt, Rainer Bruchhaus, Andreas Hilliger
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Publication number: 20040178431Abstract: An improved barrier stack for inhibiting diffusion of atoms or molecules, such as O2 is disclosed. The barrier stack is particularly useful in capacitor over plug structures to prevent plug oxidation which can adversely impact the reliability of the structures. The barrier stack includes first and second barrier layers. In one embodiment, the first barrier layer comprises first and second sub-barrier layers having mismatched grain boundaries. The sub-barrier layers are selected from, for example, Ir, Ru, Pd, Rh, or alloys thereof. By providing mismatched grain boundaries, the interface of the sub-barrier layers block the diffusion path of oxygen. To further enhance the barrier properties, the first barrier layer is passivated with O2 using, for example, a rapid thermal oxidation. The RTO forms a thin oxide layer on the surface of the first barrier layer. The oxide layer can advantageously promote mismatching of the grain boundaries of the first and second sub-barrier layer.Type: ApplicationFiled: July 10, 2003Publication date: September 16, 2004Inventors: Bum Ki Moon, Gerhard Beitel, Nicolas Nagel, Andreas Hilliger, Koji Yamakawa, Keitaro Imai
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Patent number: 6787831Abstract: An barrier stack for inhibiting diffusion of atoms or molecules, such as O2 is disclosed. The barrier slack includes first and second barrier layers formed from, for example, Ir, Ru, Pd, Rh, or alloys thereof. The first barrier layer is passivated with O2 using, for example, a rapid thermal oxidation (RTO) prior to formation of the second barrier layer. The RTO forms a thin oxide layer on the surface of the first barrier layer. The thin oxide layer passivates the grain boundaries of the first barrier layer as well as promoting mismatching of the grain boundaries of the first and second barrier layer.Type: GrantFiled: January 15, 2002Date of Patent: September 7, 2004Assignees: Infineon Technologies Aktiengesellschaft, Kabushiki Kaisha ToshibaInventors: Bum Ki Moon, Gerhard Adolf Beitel, Nicolas Nagel, Andreas Hilliger, Koji Yamakawa, Keitaro Imai
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Publication number: 20040163233Abstract: A fabrication process for ferroelectric capacitors includes forming openings 23, 30, in the device, into which electrically conductive material 28, 37 can be inserted to form electrical connections within the device. The surface of each opening is coated with a layer 24, 34 of getter material which absorbs contaminants 25, 31, 33 formed during the opening process. This means that in subsequent processing steps the contaminants do not vagabond towards the ferroelectric layers 7 of the device where they might otherwise cause damage, for example during a subsequent crystallisation stage.Type: ApplicationFiled: February 26, 2003Publication date: August 26, 2004Inventors: Stefan Gernhardt, Osamu Hidaka, Jenny Lian, Rainer Bruchhaus, Andreas Hilliger, Nicolas Nagel
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Publication number: 20040166629Abstract: A memory cell having a capacitor with top and bottom electrodes with a dielectric layer between is described. The bottom electrode is coupled to a first diffusion region of a transistor by a bottom electrode plug. A dielectric layer covers the capacitor. Above the dielectric layer is a first barrier layer. A via is created in the dielectric layer in which a plug is formed to couple to the second diffusion region. The via comprises substantially vertical sidewalls. A second barrier layer lines the sidewalls of the via. A conductive material is then deposited on the substrate, filling the via to form the plug. By providing the first and second barrier layers, the diffusion of hydrogen which can adversely impact the capacitor is reduced, thereby improving the reliability.Type: ApplicationFiled: February 25, 2003Publication date: August 26, 2004Inventors: Andreas Hilliger, Uwe Wellhausen
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Publication number: 20040149477Abstract: The present invention provides a sidewall oxygen diffusion barrier and method for fabricating the sidewall oxygen diffusion barrier to reduce the diffusion of oxygen to contact plugs during CW hole reactive ion etch processing of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence, while in another embodiment the sidewall barrier is formed by etching back an oxygen barrier.Type: ApplicationFiled: January 30, 2003Publication date: August 5, 2004Inventors: Haoren Zhuang, Ulrich Egger, Kazuhiro Tomioka, Jingyu Lian, Nicolas Nagel, Andreas Hilliger, Gerhard Beitel
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Publication number: 20040124452Abstract: A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the backside of the chip. The stress compensating layer produces a stress opposite of that produced by the IC. Thus the overall or effective stress on the substrate is reduced.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Uwe Wellhausen, Stefan Gernhardt, Rainer Bruchhaus, Andreas Hilliger, JingYu Lian, Nicolas Nagel
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Publication number: 20040104471Abstract: The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.Type: ApplicationFiled: November 29, 2002Publication date: June 3, 2004Inventors: Stefan Gernhardt, Jenny Lian, Andreas Hilliger, Rainer Bruchhaus, Uwe Wellhausen, Nicolas Nagel
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Publication number: 20040099894Abstract: First and second semiconductor regions are formed separately from each other in a semiconductor substrate. A gate electrode is formed above the semiconductor substrate which lies between the first and second semiconductor regions. An interlayer insulating film is formed on the semiconductor substrate to cover the first and second semiconductor regions and the gate electrode. First and second lower electrodes are formed on the interlayer insulating film. A first contact plug is formed in the interlayer insulating film in contact with the first lower electrode. A second contact plug is formed in the interlayer insulating film in contact with the second lower electrode. A first ferroelectric film is formed on the first lower electrode. A first upper electrode is formed on the first ferroelectric film. A second ferroelectric film is formed on the second lower electrode. A second upper electrode is formed on the second ferroelectric film.Type: ApplicationFiled: November 14, 2003Publication date: May 27, 2004Inventors: Hiroyuki Kanaya, Andreas Hilliger
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Patent number: 6724026Abstract: An improved cell design for series memory architecture is disclosed. The improved cell design facilitates the formation of capacitors using a single etch process instead of two, as conventionally required. In one embodiment, each capacitor of a capacitor pair is provided with at least one plug contacting a common diffusion region of two adjacent cell transistors. In another embodiment, a large plug with sufficient overlap to the bottom electrodes of pair of capacitors is used.Type: GrantFiled: September 19, 2002Date of Patent: April 20, 2004Assignees: Infineon Technologies Aktiengesellschaft, Kabushiki Kaisha ToshibaInventors: Michael Jacob, Andreas Hilliger, Thomas Roehr, Susumo Shuto, Toru Ozaki
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Publication number: 20040056286Abstract: An improved cell design for series memory architecture is disclosed. The improved cell design facilitates the formation of capacitors using a single etch process instead of two, as conventionally required. In one embodiment, each capacitor of a capacitor pair is provided with at least one plug contacting a common diffusion region of two adjacent cell transistors. In another embodiment, a large plug with sufficient overlap to the bottom electrodes of pair of capacitors is used.Type: ApplicationFiled: September 19, 2002Publication date: March 25, 2004Inventors: Michael Jacob, Andreas Hilliger, Thomas Roehr, Susumo Shuto, Toru Ozaki
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Publication number: 20040014310Abstract: The invention relates to a method for producing an integrated circuit comprising the following steps: preparing a semi-conductor substract (1) with a contracting circuit area (SS); providing an insulating layer (IS) on the surface of the semi-conductor substrate (1): providing a contact hole (KL) in the insulating layer (IS) for making contacting the circuit area (SS); providing an insulating spacer area (10′) in at least the area above the contact hole (KL); providing at least three trenches (BG1; BG2; BG3), the first (BG1) of which is arranged next to the contact hole (KL), a second (BG2) is disposed across the contact hole (KL) and a third (BG3) is next to the contact hole (KL). The spacer area (10′) is placed between the first and second trench (BG1; BG2) and the second and the third trench (BG2; BG3); filling the trenches (BG1; BG2; BG3) with a conductive material: and chemical-mechanical polishing of conductive material for producing three seperated trenches (BL1; BL2; BL3).Type: ApplicationFiled: April 23, 2003Publication date: January 22, 2004Inventors: Andreas Hilliger, Ralf Staub, Eike Luken
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Patent number: 6677630Abstract: First and second semiconductor regions are formed separately from each other in a semiconductor substrate. A gate electrode is formed above the semiconductor substrate which lies between the first and second semiconductor regions. An interlayer insulating film is formed on the semiconductor substrate to cover the first and second semiconductor regions and the gate electrode. First and second lower electrodes are formed on the interlayer insulating film. A first contact plug is formed in the interlayer insulating film in contact with the first lower electrode. A second contact plug is formed in the interlayer insulating film in contact with the second lower electrode. A first ferroelectric film is formed on the first lower electrode. A first upper electrode is formed on the first ferroelectric film. A second ferroelectric film is formed on the second lower electrode. A second upper electrode is formed on the second ferroelectric film.Type: GrantFiled: June 25, 2002Date of Patent: January 13, 2004Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies, AGInventors: HIroyuki Kanaya, Andreas Hilliger
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Publication number: 20030234411Abstract: First and second semiconductor regions are formed separately from each other in a semiconductor substrate. A gate electrode is formed above the semiconductor substrate which lies between the first and second semiconductor regions. An interlayer insulating film is formed on the semiconductor substrate to cover the first and second semiconductor regions and the gate electrode. First and second lower electrodes are formed on the interlayer insulating film. A first contact plug is formed in the interlayer insulating film in contact with the first lower electrode. A second contact plug is formed in the interlayer insulating film in contact with the second lower electrode. A first ferroelectric film is formed on the first lower electrode. A first upper electrode is formed on the first ferroelectric film. A second ferroelectric film is formed on the second lower electrode. A second upper electrode is formed on the second ferroelectric film.Type: ApplicationFiled: June 25, 2002Publication date: December 25, 2003Inventors: Hiroyuki Kanaya, Andreas Hilliger