Patents by Inventor Andreas Hinrich

Andreas Hinrich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230197665
    Abstract: The invention relates to a metal layer stack for use in electronic components, in particular as a spacer in power electronic components, comprising n bulk metal layers and n or n+1 contact material layers, wherein the bulk metal layers and the contact material layers are stacked in an alternating manner and n is at least two. Additionally, the invention relates to a process for preparing the metal layer stack and a semiconductor module comprising such a metal layer stack.
    Type: Application
    Filed: December 16, 2022
    Publication date: June 22, 2023
    Inventor: Andreas HINRICH
  • Patent number: 11440310
    Abstract: One aspect relates to a method for producing a substrate adapter for the connecting to an electronic component, including arranging at least one contacting material layer between at least one side of a carrier and a surface of a substrate such that the contacting material layer has at least one predetermined breaking point, and joining the carrier and the substrate to the contacting material layer. One aspect also relates to a substrate adapter for connecting to an electronic component.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: September 13, 2022
    Assignee: Heraeus Deutschland GmbH & Co. KG
    Inventors: Andreas Steffen Klein, Andreas Hinrich, Michael Schaefer, Yvonne Loewer, Wolfgang Schmitt, Michael Lemmer
  • Publication number: 20200180294
    Abstract: One aspect relates to a method for producing a substrate adapter for the connecting to an electronic component, including arranging at least one contacting material layer between at least one side of a carrier and a surface of a substrate such that the contacting material layer has at least one predetermined breaking point, and joining the carrier and the substrate to the contacting material layer. One aspect also relates to a substrate adapter for connecting to an electronic component.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 11, 2020
    Applicant: Heraeus Deutschland GmbH & Co. KG
    Inventors: Andreas Steffen Klein, Andreas Hinrich, Michael Schaefer, Yvonne Loewer, Wolfgang Schmitt, Michael Lemmer
  • Patent number: 10622331
    Abstract: One aspect relates to a method for manufacturing a substrate assembly for attachment to an electronic component A substrate is provided with a first side and a second side. A contact material layer is applied to the first side of the substrate. A pre-fixing agent is applied at least to sections of a side of the contact material layer facing away from the substrate.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: April 14, 2020
    Assignee: Heraeus Deutschland GmbH & Co. KG
    Inventors: Andreas Hinrich, Susanne Duch, Anton Miric, Michael Schäfer, Christian Bachmann, Holger Ulrich, Frank Osterwald, David Benning, Jacek Rudzki, Lars Paulsen, Frank Schefuss, Martin Becker
  • Patent number: 10347566
    Abstract: A carrier and the clip are used to produce a packaging having a lead frame by connection to the chip using sintering of the solidified sintering pastes in one work step. The carrier may be a lead frame and a clip for at least one semiconductor element has at least one functional surface for connecting to the semiconductor element and a plurality of connections. The material of the earlier or of the clip includes a metal and a layer made of a solidified sintering paste. The sintering paste may contain silver and/or a silver compound. The sintering paste is arranged on the functional surface. The carrier or clip and the layer made of sintering paste form an intermediate product that can be connected to the semiconductor element.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: July 9, 2019
    Assignee: HERAEUS DEUTSCHLAND GMBH & CO. KG
    Inventors: Michael Benedikt, Thomas Krebs, Michael Schäfer, Wolfgang Schmitt, Andreas Hinrich, Andreas Klein, Alexander Brand, Martin Bleifuss
  • Publication number: 20180286831
    Abstract: One aspect relates to a method for manufacturing a substrate assembly for attachment to an electronic component A substrate is provided with a first side and a second side. A contact material layer is applied to the first side of the substrate. A pre-fixing agent is applied at least to sections of a side of the contact material layer facing away from the substrate.
    Type: Application
    Filed: September 28, 2016
    Publication date: October 4, 2018
    Applicant: Heraeus Deutschland GmbH & Co. KG
    Inventors: Andreas HINRICH, Susanne DUCH, Anton MIRIC, Michael SCHÄFER
  • Publication number: 20170117209
    Abstract: A carrier and the clip are used to produce a packaging having a lead frame by connection to the chip using sintering of the solidified sintering pastes in one work step. The carrier may be a lead frame and a clip for at least one semiconductor element has at least one functional surface for connecting to the semiconductor element and a plurality of connections. The material of the carrier or of the clip includes a metal and a layer made of a solidified sintering paste. The sintering paste may contain silver and/or a silver compound. The sintering paste is arranged on the functional surface. The carrier or clip and the layer made of sintering paste form an intermediate product that can be connected to the semiconductor element.
    Type: Application
    Filed: March 26, 2015
    Publication date: April 27, 2017
    Applicant: HERAEUS DEUTSCHLAND GMBH & CO. KG
    Inventors: Michael BENEDIKT, Thomas KREBS, Michael SCHÄFER, Wolfgang SCHMITT, Andreas HINRICH, Andreas KLEIN, Alexander BRAND, Martin BLEIFUSS
  • Publication number: 20170110390
    Abstract: The invention relates to a support and/or clip for at least one semiconductor element with at least one functional surface (10) for connecting to the semiconductor element. The invention is further characterized by at least one solder resist cavity (12) with at least one flank wall (13), in particular a straight flank wall (13), and a delimiting edge (14) which adjoins the flank wall (13) and delimits the functional surface (10) at least on one side. The delimiting edge (14) forms a protrusion (15) which protrudes past the functional surface (10) in order to retain solder, and/or the flank wall (13) forms an undercut (16) for retaining solder at the delimiting edge (14).
    Type: Application
    Filed: March 26, 2015
    Publication date: April 20, 2017
    Applicant: HERAEUS DEUTSCHLAND GMBH & CO. KG
    Inventors: Andreas HINRICH, Reinhard DITZEL, Andreas KLEIN
  • Publication number: 20130215584
    Abstract: The invention relates to methods for producing a laminate for contacting an electronic component, in which an insulating layer is arranged between first and second metal layers. The method includes contacting the metal layers to each other in a contact region, generating a recess in the insulating layer, laminating the metal layers to the insulating layer, generating a notch for accommodating the electronic component in the contact region in the first metal layer, inserting the electronic component in a depression in the laminate formed through a notch and recess. The electronic component is connected in a conductive manner to the second metal layer, such that an entire circumference of the electronic component is accommodated in the recess and/or notch, and at least part of the height of the electronic component is accommodated in the notch and/or recess. The invention also relates to such a laminate for contacting an electronic component.
    Type: Application
    Filed: October 24, 2011
    Publication date: August 22, 2013
    Applicant: HERAEUS MATERIALS TECHNOLOGY GMBH & CO. KG
    Inventors: Andreas Klein, Eckhard Ditzel, Frank Krüger, Wulf Kock, Andreas Hinrich