Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications.

Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications.

Abstract: The electronic device comprises a thin-film transistor (10) and can be obtained from two substrates (1, 11). In order to preclude delamination at a non-adhesive interface between a metal pattern (24, 29) and an organic layer (4), the metal pattern (24, 29) comprises apertures (30). Through these apertures (30), adhesion between the organic layer (4, 5) and organic material at the surface (111) of one of the substrates (11) can be brought about. The electronic device can be manufactured by use of microcontact printing.

Abstract: A vertical interconnect (15) in an electronic device (10) is manufactured non-photolithographically. This is done by modifying a surface (20,30) of either a metal layer (3) or an intermediate layer of an electrically insulating material (21), and subsequently depositing a composition with a first and a second polymer. Phase separation of the two polymers will lead to a first (6) and a second sub-layer (7), of which the first sub-layer (6) is removed. An upper layer (9) of electrically conducting material can be deposited then or after a further etching step. This results in the vertical interconnect (15).

Abstract: The electronic device comprises a thin-film transistor (10) and can be obtained from two substrates (1, 11). In order to preclude delamination at a non-adhesive interface between a metal pattern (24, 29) and an organic layer (4), the metal pattern (24, 29) comprises apertures (30). Through these apertures (30), adhesion between the organic layer (4, 5) and organic material at the surface (111) of one of the substrates (11) can be brought about. The electronic device can be manufactured by means of microcontact printing.

Abstract: The electronic device (1) has a layer (11) of a material comprising a first and a second element. This material has an amorphous and a crystalline state. A transition from the amorphous to the crystalline state can be effected by heating of the material to above a crystallization temperature, for example with a laser. As a result, the layer (11) has a first electrically conducting areas (21), comprising the material in the crystalline state, which are insulated from each other by the first electrically insulating area (23), comprising the material in the amorphous state. The layer (11) may be present as an interconnect layer, but also as a covering layer. Preferably, the material is aluminum-germanium. In the method of patterning a layer (11), electrically conductive areas of the layer can be strengthened by electroplating.

Abstract: A vertical interconnect (15) in an electronic device (10) is manufactured non-photolithographically. This is done by modifying a surface (20,30) of either a metal layer (3) or an intermediate layer of an electrically insulating material (21), and subsequently depositing a composition with a first and a second polymer. Phase separation of the two polymers will lead to a first (6) and a second sub-layer (7), of which the first sub-layer (6) is removed. An upper layer (9) of electrically conducting material can be deposited then or after a further etching step. This results in the vertical interconnect (15).

Abstract: In a method of manufacturing a semiconductor device comprising a semiconductor body 1 which is provided at a surface 2 with a transistor comprising a gate structure 21, a patterned layer 10 is applied defining the area of the gate structure 21. Subsequently, a dielectric layer 18 is applied in such a way, that the thickness of the dielectric layer 18 next to the patterned layer 10 is substantially equally large or larger than the height of the patterned layer 10, which dielectric layer 18 is removed over part of its thickness until the patterned layer 10 is exposed. Then, the patterned layer 10 is subjected to a material removing treatment, thereby forming a recess 19 in the dielectric layer 18, and a contact window 28,29 is provided in the dielectric layer.

Abstract: The electronic device (1) has a layer (11) of a material comprising a first and a second element. This material has an amorphous and a crystalline state. A transition from the amorphous to the crystalline state can be effected by heating of the material to above a crystallization temperature, for example with a laser. As a result, the layer (11) has a first electrically conducting areas (21), comprising the material in the crystalline state, which are insulated from each other by the first electrically insulating area (23), comprising the material in the amorphous state. The layer (11) may be present as an interconnect layer, but also as a covering layer. Preferably, the material is aluminum-germanium. In the method of patterning a layer (11), electrically conductive areas of the layer can be strengthened by electroplating.

Abstract: The passive component (1) has a first part (22) of a material with a first resistance value, which value can be lowered to a second value by laser trimming. The second value is at most one tenth of the first value and preferably less. The material crystallizes in a laser trimming process, which locally heats the material to at least a transition temperature. The material contains at least two different elements, which are preferably aluminum and germanium. The passive component (1) may be, for example, a resistor or a capacitor and may be part of a thin-film network of resistors, capacitors and/or inductors. In a resistor, it is preferred to have a second part (4) which contains a different resistance material with a resistance value lower than the first value and preferably higher than the second value.

Abstract: The electronic device (1) has a layer (11) of a material comprising a first and a second element. This material has an amorphous and a crystalline state. A transition from the amorphous to the crystalline state can be effected by heating of the material to above a crystallization temperature, for example with a laser. As a result, the layer (11) has a first electrically conducting areas (21), comprising the material in the crystalline state, which are insulated from each other by the first electrically insulating area (23), comprising the material in the amorphous state. The layer (11) may be present as an interconnect layer, but also as a covering layer. Preferably, the material is aluminum-germanium. In the method of patterning a layer (11), electrically conductive areas of the layer can be strengthened by electroplating.

Abstract: In a method of manufacturing a semiconductor device comprising a semiconductor body 1 which is provided at a surface 2 with a transistor comprising a gate structure 21, a patterned layer 10 is applied defining the area of the gate structure 21. Subsequently, a dielectric layer 18 is applied in such a way, that the thickness of the dielectric layer 18 next to the patterned layer 10 is substantially equally large or larger than the height of the patterned layer 10, which dielectric layer 18 is removed over part of its thickness until the patterned layer 10 is exposed. Then, the patterned layer 10 is subjected to a material removing treatment, thereby forming a recess 19 in the dielectric layer 18, and a contact window 28,29 is provided in the dielectric layer.

Abstract: In a method of manufacturing a semiconductor device comprising a semiconductor body 1 which is provided at a surface 2 with a transistor comprising a gate structure 21, a patterned layer 10 is applied defining the area of the gate structure 21. Subsequently, a dielectric layer 18 is applied in such a way, that the thickness of the dielectric layer 18 next to the patterned layer 10 is substantially equally large or larger than the height of the patterned layer 10, which dielectric layer 18 is removed over part of its thickness until the patterned layer 10 is exposed. Then, the patterned layer 10 is subjected to a material removing treatment, thereby forming a recess 19 in the dielectric layer 18, and a contact window 28,29 is provided in the dielectric layer.

Abstract: The passive component (1) has a first part (22) of a material with a first resistance value, which value can be lowered to a second value by laser trimming. The second value is at most one tenth of the first value and preferably less. Said material crystallizes in a laser trimming process, which locally heats the material to at least a transition temperature. Said material contains at least two different elements, which are preferably aluminum and germanium.

Abstract: The electronic device (1) has a layer (11) of a material comprising a first and a second element. This material has an amorphous and a crystalline state. A transition from the amorphous to the crystalline state can be effected by heating of the material to above a crystallization temperature, for example with a laser. As a result, the layer (11) has a first electrically conducting areas (21), comprising the material in the crystalline state, which are insulated from each other by the first electrically insulating area (23), comprising the material in the amorphous state. The layer (11) may be present as an interconnect layer, but also as a covering layer. Preferably, the material is aluminum-germanium. In the method of patterning a layer (11), electrically conductive areas of the layer can be strengthened by electroplating.

Abstract: In a method of manufacturing a semiconductor device comprising a semiconductor body 1 which is provided at a surface 2 with a transistor comprising a gate structure 21, a patterned layer 10 is applied defining the area of the gate structure 21. Subsequently, a dielectric layer 18 is applied in such a way, that the thickness of the dielectric layer 18 next to the patterned layer 10 is substantially equally large or larger than the height of the patterned layer 10, which dielectric layer 18 is removed over part of its thickness until the patterned layer 10 is exposed. Then, the patterned layer 10 is subjected to a material removing treatment, thereby forming a recess 19 in the dielectric layer 18, and a contact window 28, 29 is provided in the dielectric layer.