Abstract: Three state latch. In accordance with a first embodiment, an electronic circuit includes a single latch having three stable states. The electronic circuit may be configured so that all three outputs reflect a change at any one input in not more than three gate delays. The electronic circuit may further be configured so that when all inputs are set to one, a previous state of the latch is retained and output on the outputs.

Abstract: Three state latch. In accordance with a first embodiment, an electronic circuit includes n pairs of cascaded logical gates. Each of the n pairs of cascaded logical gates includes a first logical gate including n?1 first gate inputs and one first gate output, and a second logical gate including two second gate inputs and one second gate output. One of the second gate inputs is coupled to the first gate output. The second gate output is cross coupled to one of the first gate inputs of all other the pairs of cascaded logical gates, and n is greater than 2.

Abstract: Three state latch. In accordance with a first embodiment, an electronic circuit includes n pairs of cascaded logical gates. Each of the n pairs of cascaded logical gates includes a first logical gate including n?1 first gate inputs and one first gate output, and a second logical gate including two second gate inputs and one second gate output. One of the second gate inputs is coupled to the first gate output. The second gate output is cross coupled to one of the first gate inputs of all other the pairs of cascaded logical gates, and n is greater than 2.

Abstract: Handshaking sense amplifier. In accordance with a first embodiment, an electronic circuit includes a sense amplifier configured to differentially sense contents of a memory cell. The circuit also includes a self-timing circuit configured to detect a completion of evaluation by the sense amplifier; and to initiate a subsequent memory operation responsive to the completion. A completion of evaluation may not be aligned with a clock edge.

Abstract: In accordance with a first embodiment, an electronic circuit includes a single latch having three stable states. The electronic circuit may be configured so that all three outputs reflect a change at any one input in not more than three gate delays. The electronic circuit may further be configured so that when all inputs are set to one, a previous state of the latch is retained and output on the outputs.

Abstract: Pipelined one cycle throughput for single-port 6T RAM. In accordance with a first embodiment, an electronic circuit is configured to perform consecutive read accesses using one sense amplifier. The electronic circuit includes circuitry configured to precharge the sense amplifier, circuitry configured to precharge a sense node coupled to the sense amplifier, and circuitry configured to develop the sense node. The electronic circuit also includes circuitry configured to evaluate the sense node to read a first bit, and circuitry configured to detect a completion of an evaluate operation on the sense nodes. The consecutive read accesses may be conducted with single cycle throughput of a synchronizing clock signal. The circuitry configured to detect a completion of an evaluate operation on the sense nodes may include a three state latch.

Abstract: Handshaking sense amplifier. In accordance with a first embodiment, an electronic circuit includes a sense amplifier configured to differentially sense contents of a memory cell. The circuit also includes a self-timing circuit configured to detect a completion of evaluation by the sense amplifier; and to initiate a subsequent memory operation responsive to the completion. A completion of evaluation may not be aligned with a clock edge.