Patents by Inventor Andreas Jörn Leistner

Andreas Jörn Leistner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10483911
    Abstract: Various designs for MOS transistor-based RF switch topologies for high speed capacitive tuning of oscillators switch circuits include a main switch device comprising a gate connected to a control terminal, a drain connected to a first terminal that is connected to the first capacitor, and a source connected to a second terminal that is connected to the second capacitor. The switch further comprises a first NMOS device having a gate connected to the main switch device gate, a source connected to a ground, and a drain connected to the first terminal. The switch further comprises a second NMOS device having a gate connected to the main switch device gate, a source connected to a ground, and a drain connected to the second terminal. The switch further comprises a pair of PMOS devices each having drains connected respectively to the first and second terminals.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Svetozar Broussev, Andreas Jörn Leistner, Andreas Roithmeier, Thomas Gustedt
  • Publication number: 20180083573
    Abstract: Various designs for MOS transistor-based RF switch topologies for high speed capacitive tuning of oscillators switch circuits include a main switch device comprising a gate connected to a control terminal, a drain connected to a first terminal that is connected to the first capacitor, and a source connected to a second terminal that is connected to the second capacitor. The switch further comprises a first NMOS device having a gate connected to the main switch device gate, a source connected to a ground, and a drain connected to the first terminal. The switch further comprises a second NMOS device having a gate connected to the main switch device gate, a source connected to a ground, and a drain connected to the second terminal. The switch further comprises a pair of PMOS devices each having drains connected respectively to the first and second terminals.
    Type: Application
    Filed: December 28, 2016
    Publication date: March 22, 2018
    Inventors: Svetozar Broussev, Andreas Jörn Leistner, Andreas Roithmeier, Thomas Gustedt
  • Patent number: 9800439
    Abstract: Apparatus and methods for disrupting or preventing periodicity in DTC circuits are provided. In an example, a communication circuit can include a digital-to-time converter (DTC) and a processing path coupled to the DTC. The DTC can be configured to receive reference information, modulation information and first dither information, and to provide a modulated signal using the reference information, the modulation information and the first dither information. The processing path can be configured to receive second dither information and to cancel the first dither information using the second dither information, wherein the DTC is configured to disrupt processing periodicity of the communication circuit using the first dither information.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: October 24, 2017
    Assignee: Intel Corporation
    Inventors: Andreas Jörn Leistner, Georgios Palaskas
  • Publication number: 20160182262
    Abstract: Apparatus and methods for disrupting or preventing periodicity in DTC circuits are provided. In an example, a communication circuit can include a digital-to-time converter (DTC) and a processing path coupled to the DTC. The DTC can be configured to receive reference information, modulation information and first dither information, and to provide a modulated signal using the reference information, the modulation information and the first dither information. The processing path can be configured to receive second dither information and to cancel the first dither information using the second dither information, wherein the DTC is configured to disrupt processing periodicity of the communication circuit using the first dither information.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: Andreas Jörn Leistner, Georgios Palaskas