Patents by Inventor Andreas Jon Gotterba

Andreas Jon Gotterba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Slew signal shaper circuit using two signal paths
    Patent number: 11854660
    Abstract: To mitigate pulse shape degradation along a signal route, the signal is driven from two ends. One end of the route is loaded and the other is relatively unloaded. The loaded route and unloaded route may traverse two different metal layers on a printed circuit board. The two routes may thus be related such that the unloaded route has less RC distortion effects on the signal than does the loaded route.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: December 26, 2023
    Assignee: NVIDIA CORP.
    Inventors: Lalit Gupta, Andreas Jon Gotterba, Jesse Wang
  • Area efficient memory cell read disturb mitigation
    Patent number: 11804262
    Abstract: A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: October 31, 2023
    Assignee: NVIDIA CORP.
    Inventors: Lalit Gupta, Andreas Jon Gotterba, Jesse Wang, Stefan P Sywyk
  • KEEPER-FREE VOLATILE MEMORY SYSTEM
    Publication number: 20230267992
    Abstract: A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Applicant: NVIDIA Corp.
    Inventors: Lalit Gupta, Stefan P. Sywyk, Andreas Jon Gotterba, Jesse Wang
  • SLEW SIGNAL SHAPER CIRCUIT
    Publication number: 20230197127
    Abstract: To mitigate pulse shape degradation along a signal route, the signal is driven from two ends. One end of the route is loaded and the other is relatively unloaded. The loaded route and unloaded route may traverse two different metal layers on a printed circuit board. The two routes may thus be related such that the unloaded route has less RC distortion effects on the signal than does the loaded route.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Applicant: NVIDIA Corp.
    Inventors: Lalit Gupta, Andreas Jon Gotterba, Jesse Wang
  • AREA EFFICIENT MEMORY CELL READ DISTURB MITIGATION
    Publication number: 20220406371
    Abstract: A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Applicant: NVIDIA Corp.
    Inventors: Lalit Gupta, Andreas Jon Gotterba, Jesse Wang, Stefan P. Sywyk