Patents by Inventor Andreas K. Roelofs

Andreas K. Roelofs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods for top-down fabrication of wafer scale TMDC monolayers
    Patent number: 9809903
    Abstract: A method of forming a TMDC monolayer comprises providing a multi-layer transition metal dichalcogenide (TMDC) film. The multi-layer TMDC film comprises a plurality of layers of the TMDC. The multi-layer TMDC film is positioned on a conducting substrate. The conducting substrate is contacted with an electrolyte solution. A predetermined electrode potential is applied on the conducting substrate and the TMDC monolayer for a predetermined time. A portion of the plurality of layers of the TMDC included in the multi-layer TMDC film is removed by application of the predetermined electrode potential, thereby leaving a TMDC monolayer film positioned on the conducting substrate.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 7, 2017
    Assignee: UChicago Argonne, LLC
    Inventors: Saptarshi Das, Mrinal K. Bera, Andreas K. Roelofs, Mark Antonio
  • SYSTEMS AND METHODS FOR TOP-DOWN FABRICATION OF WAFER SCALE TMDC MONOLAYERS
    Publication number: 20170253996
    Abstract: A method of forming a TMDC monolayer comprises providing a multi-layer transition metal dichalcogenide (TMDC) film. The multi-layer TMDC film comprises a plurality of layers of the TMDC. The multi-layer TMDC film is positioned on a conducting substrate. The conducting substrate is contacted with an electrolyte solution. A predetermined electrode potential is applied on the conducting substrate and the TMDC monolayer for a predetermined time. A portion of the plurality of layers of the TMDC included in the multi-layer TMDC film is removed by application of the predetermined electrode potential, thereby leaving a TMDC monolayer film positioned on the conducting substrate.
    Type: Application
    Filed: March 4, 2016
    Publication date: September 7, 2017
    Applicant: UChicago Argonne, LLC
    Inventors: Saptarshi Das, Mrinal K. Bera, Andreas K. Roelofs, Mark Antonio
  • Quiescent testing of non-volatile memory array
    Patent number: 8526252
    Abstract: A method and apparatus for testing an array of non-volatile memory cells, such as a spin-torque transfer random access memory (STRAM). In some embodiments, an array of memory cells having a plurality of unit cells with a resistive sense element and a switching device has a row decoder and a column decoder connected to the plurality of unit cells. A test circuitry sends a non-operational test pattern through the array via the row and column decoders with a quiescent supply current to identify defects in the array of memory cells.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: September 3, 2013
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Alan Xuguang Wang, Haiwen Xi, Wenzhong Zhu, Andreas K. Roelofs
  • Quiescent Testing of Non-Volatile Memory Array
    Publication number: 20100238700
    Abstract: A method and apparatus for testing an array of non-volatile memory cells, such as a spin-torque transfer random access memory (STRAM). In some embodiments, an array of memory cells having a plurality of unit cells with a resistive sense element and a switching device has a row decoder and a column decoder connected to the plurality of unit cells. A test circuitry sends a non-operational test pattern through the array via the row and column decoders with a quiescent supply current to identify defects in the array of memory cells.
    Type: Application
    Filed: March 17, 2009
    Publication date: September 23, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Hai Li, Yiran Chen, Alan Xuguang Wang, Haiwen Xi, Wenzhong Zhu, Andreas K. Roelofs