Abstract: A microprocessor system (50) for controlling or regulating at least partly safety-critical processes, comprising two central processing units (1, 2) integrated in a chip housing, a first and a second bus system, at least one full memory (7) on the first bus system, at least one test data store (51) on the second bus system, which has a reduced store coverage compared to the full memory on the first bus system and in which test data are stored which are connected to data of the memory (7) on the first bus system, and the bus systems comprise comparison and/or driver components which allow the data interchange and/or comparison of data between the two bus systems, and a hardware test data generator (4) is arranged at least on the second bus system, in which case at least part of the full memory on the first bus is additionally backed up using another test data store (5) and test data on the first bus. The invention further relates to the use of the above microprocessor system in motor vehicle controllers.

Abstract: An integrated circuit arrangement on a common chip or chip support, for safety critical applications, in particular for use in control and regulation units for a motor vehicle braking system, including at least one microprocessor system module, which has at least one core processor, provided with at least one ROM and at least one RAM, at least one power module for controlling external users and at least one monitoring module for monitoring at least parts and/or part systems of the circuit arrangement, the circuit arrangement including at least one temperature sensor for recording a chip temperature.

Abstract: A memory mapping system is connectable to a multi-processing arrangement. The multi-processing arrangement includes a first processing unit and a second processing unit. The memory mapping system includes a main memory to which the second processing unit does not have write access, the main memory including a first memory section and a second memory section. An associated memory is associated with the second memory section. The associated memory includes a memory section to which the second processing unit has write access. A consistency control unit can maintaining consistency between data stored in the associated memory and data stored in the second memory section.

Abstract: The invention relates to a microprocessor system (60) for controlling and/or regulating at least partly security-critical processes, which system comprises two central processing units (1, 2) integrated into a chip housing, a first and a second bus system, at least one complete memory (7) on the first bus system, and check data in one or more check data memories, said data being related to data of the memory in the first bus system. The check data memory is smaller than the complete memory. The bus systems comprise comparative and/or driver components which facilitate data exchange and/or comparison of data between the two bus systems. The one or more check data memories are arranged on the first bus system. On the second bus system, neither a check data memory nor a memory safeguarding data of the memory on the first bus is used. The invention also relates to the use of the inventive microprocessor system in automotive control devices.

Abstract: A microprocessor includes a pipeline microarchitecture and a pipeline bubble detection device. The pipeline bubble detection device has a minimum execution clock cycle ascertainment unit for ascertaining a minimum or optimum number of execution clock cycles for one or more program commands which pass through the pipeline microarchitecture or are handled by the pipeline microarchitecture.

Abstract: A memory mapping system is connectable to a multi-processing arrangement. The multi-processing arrangement includes a first processing unit and a second processing unit. The memory mapping system includes a main memory to which the second processing unit does not have write access, the main memory including a first memory section and a second memory section. An associated memory is associated with the second memory section. The associated memory includes a memory section to which the second processing unit has write access. A consistency control unit can maintaining consistency between data stored in the associated memory and data stored in the second memory section.

Abstract: The invention relates to a microprocessor system (60) for controlling and/or regulating at least partly security-critical processes, which system comprises two central processing units (1, 2) integrated into a chip housing, a first and a second at least one complete memory (7) on the first bus system, and check data in one or more check data memories, said data being related to data of the memory in the first bus system. The check data memory is smaller than the complete memory. The bus systems comprise comparative and/or driver components which facilitate data exchange and/or comparison of data between the two bus systems. The one or more check data memories are arranged on the first bus system. On the second bus system, neither a check data memory nor a memory safeguarding data of the memory on the first bus is used. The invention also relates to the use of the inventive microprocessor system in automotive control devices.

Abstract: An automated method for producing integrated circuit arrangements for automotive vehicle control systems provides at least two logically isolated subsystems (5, 6) and, in addition to the logical isolation, effects a spatial (physical) isolation of the subsystems on the surface available on the circuit arrangement.

Abstract: Disclosed is a system and method for the detection and/or correction of memory access errors in computer systems. Test data (P) is generated in addition to data (D) which is to be secured, using the latter data (D), and is stored inside a memory (4) in such a fashion that a particularly high rate of reliability in error detection and correction can be achieved. To this end, in addition to the data (D) to be secured, the data's addresses are taken into account according to the present system and method when generating the test data (P).

Abstract: The invention discloses an analysis device for an embedded system (9) comprising a CPU (1), a CPU bus (2) and a memory (3). The embedded system has at least one communication module (4) for the input or output of analysis data by way of a test interface (5). The communication module permits the internal memory and the input and output access operations of the embedded system to be monitored and/or logged without using the clock cycles of the CPU (1).

Abstract: The present invention relates to a method for producing integrated circuit arrangements for automotive vehicle control systems by establishing a layout using an automated method, wherein at least two logically isolated subsystems (5, 6) are provided and, in addition to the logical isolation, a spatial (physical) isolation of the subsystems is effected on the surface available on the circuit arrangement.