Patents by Inventor Andreas Kuehlmann

Andreas Kuehlmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12387021
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing information flow analysis on hardware designs to identify vulnerabilities. One of the methods includes generating input signals and feeding the generated input signals into the modified hardware design to generate a plurality of information flow signals, wherein the information flow signals each associate a respective input signal with a location in the modified hardware design to which the input signal was able to reach through logic circuitry of the modified hardware design. The generated information flow signals are evaluated according to one or more security criteria to generate security results. One or more security related applications are performed to generate information representing aspects of the design that are vulnerable to insecure behavior.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: August 12, 2025
    Assignee: Cycuity, Inc.
    Inventors: Jason K. Oberg, Alric Althoff, Andreas Kuehlmann
  • Publication number: 20230394207
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing information flow analysis on hardware designs to identify vulnerabilities. One of the methods includes generating input signals and feeding the generated input signals into the modified hardware design to generate a plurality of information flow signals, wherein the information flow signals each associate a respective input signal with a location in the modified hardware design to which the input signal was able to reach through logic circuitry of the modified hardware design. The generated information flow signals are evaluated according to one or more security criteria to generate security results. One or more security related applications are performed to generate information representing aspects of the design that are vulnerable to insecure behavior.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Inventors: Jason K. Oberg, Alric Althoff, Andreas Kuehlmann
  • Publication number: 20230394158
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing information flow analysis on hardware designs to identify vulnerabilities. One of the methods includes receiving a set of security rules for a hardware design having information flow tracking logic. An information flow analysis process is performed to determine where design assets specified by the security rules flow in the hardware design. A user interface presentation is generated that presents a listing of modules through which the design asset flowed and an indication of when a flow of the design asset violated one or more of the security rules.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Inventors: Jason K. Oberg, Alric Althoff, Andreas Kuehlmann
  • Patent number: 10713069
    Abstract: A method to emulate a system represented by one or more of hardware portions and software portions is described. The method comprises determining whether a subset of the one or more hardware portions and software portions have been tested, and identifying whether the system has performed to a specification based on the testing. The method further comprising, when the system has not performed to the specification, determining one or more of the hardware and software portions to update for retesting.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: July 14, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Marat Boshernitsan, Scott McPeak, Andreas Kuehlmann, Roger H. Scott, Andy Chou, Kit Transue
  • Patent number: 9836390
    Abstract: A method is provided to evaluate impact of a change to code of a depended upon component of a system stored in a computer readable storage device, upon a dependent component of the system, the method comprising: identifying a dependency relationship between a first component stored in a computer readable storage device and a second component stored in the computer readable storage device; in response to a determination that the second component depends upon the first component, configuring a computer system to obtain a first property evaluation corresponding to the first component; and in response to obtaining the first property evaluation corresponding to the first component, configuring the computer system to associate the first property evaluation with the second component, and obtain a second property evaluation corresponding to the second component, wherein the second component is associated with the first property evaluation.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: December 5, 2017
    Assignee: Synopsys, Inc.
    Inventors: Marat Boshernitsan, Andreas Kuehlmann, Scott McPeak, Philip Chong, Tobias Welp
  • Patent number: 9612943
    Abstract: A method is provided to prioritize testing of computer program code comprising: determining first test coverages of items within a first source code version for multiple tests; storing in a non-transitory storage device, a first history that indicates the determined first test coverages of the items within the first source code version; identifying occurrences of the items within a second source code version; determining first weights associated with tests, wherein a respective weight associated with a respective test is indicative of a respective number of respective items within the second source code version that are covered by the respective associated test according to the first history; and prioritizing the multiple respective tests based at least in part upon the determined first weights.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: April 4, 2017
    Assignee: Synopsys, Inc.
    Inventors: Marat Boshernitsan, Andreas Kuehlmann
  • Publication number: 20170017506
    Abstract: A method to emulate a system represented by one or more of hardware portions and software portions is described. The method comprises determining whether a subset of the one or more hardware portions and software portions have been tested, and identifying whether the system has performed to a specification based on the testing. The method further comprising, when the system has not performed to the specification, determining one or more of the hardware and software portions to update for retesting.
    Type: Application
    Filed: April 18, 2016
    Publication date: January 19, 2017
    Inventors: Marat Boshernitsan, Scott McPeak, Andreas Kuehlmann, Roger H. Scott, Andy Chou, Kit Transue, Kenneth S. McElvain, Igor L. Markov
  • Patent number: 9317399
    Abstract: A method is provided to evaluate tests of computer program code comprising: configuring a computer to produce, in a computer readable storage device, a code filter to indicate one or more respective portions of the computer program code to respectively either omit from or to include in a determination of adequacy of results; and comparing test results with the computer program code with the one or more respective portions filtered using the code filter to respectively either omit the respective portions from or include the respective portions in the determination as indicated by the code filter.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 19, 2016
    Assignee: Synopsys, Inc.
    Inventors: Marat Boshernitsan, Scott McPeak, Andreas Kuehlmann, Roger H. Scott, Andy C. Chou, Kit Transue
  • Publication number: 20150317236
    Abstract: A method is provided method to evaluate impact of a change in code of a depended upon component of a system stored in a non-transitory computer readable storage device, upon a dependent component of the system, the method comprising: identifying a dependency relationship between a first component stored in a storage device and a second component stored in the storage device; in response to a determination that the second component depends upon the first component, configuring a computer system to obtain a first property evaluation corresponding to the first component; and in response to obtaining the first property evaluation corresponding to the first component, configuring the computer system to associate the first property evaluation with the second component, and determine a second property evaluation corresponding to the second component, is the second component being associated with the first property evaluation.
    Type: Application
    Filed: May 11, 2015
    Publication date: November 5, 2015
    Inventors: Marat Boshernitsan, Andreas Kuehlmann, Scott McPeak, Philip Chong, Tobias Welp
  • Patent number: 9032376
    Abstract: A method is provided to evaluate impact of a change in code of a depended upon component of a system stored in a computer readable storage device, upon a dependent component of the system, the method comprising: identifying a dependency relationship between a first component stored in a computer readable storage device and a second component stored in the computer readable storage device; in response to a determination that the second component depends upon the first component, configuring a computer system to obtain a first property evaluation corresponding to the first component; and in response to obtaining the first property evaluation corresponding to the first component, configuring the computer system to associate the first property evaluation with the second component, and obtain a second property evaluation corresponding to the second component, wherein the second component is associated with the first property evaluation.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 12, 2015
    Assignee: Synopsys, Inc.
    Inventors: Marat Boshernitsan, Andreas Kuehlmann, Scott McPeak, Philip Chong, Tobias Welp
  • Publication number: 20150007140
    Abstract: A method is provided to prioritize testing of computer program code comprising: determining first test coverages of items within a first source code version for multiple tests; storing in a non-transitory storage device, a first history that indicates the determined first test coverages of the items within the first source code version; identifying occurrences of the items within a second source code version; determining first weights associated with tests, wherein a respective weight associated with a respective test is indicative of a respective number of respective items within the second source code version that are covered by the respective associated test according to the first history; and prioritizing the multiple respective tests based at least in part upon the determined first weights.
    Type: Application
    Filed: September 26, 2013
    Publication date: January 1, 2015
    Applicant: Coverity, Inc.
    Inventors: Marat Boshernitsan, Andreas Kuehlmann
  • Patent number: 8862439
    Abstract: In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a solution. If the search finds a numeric assignment that satisfies each and every one of the one or more numeric formulas, it indicates that a functional property of the system is violated.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: October 14, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Andreas Kuehlmann, Kenneth L. McMillan, Shmuel Sagiv
  • Publication number: 20140130020
    Abstract: A method is provided method to evaluate impact of a change in code of a depended upon component of a system stored in a non-transitory computer readable storage device, upon a dependent component of the system, the method comprising: identifying a dependency relationship between a first component stored in a storage device and a second component stored in the storage device; in response to a determination that the second component depends upon the first component, configuring a computer system to obtain a first property evaluation corresponding to the first component; and in response to obtaining the first property evaluation corresponding to the first component, configuring the computer system to associate the first property evaluation with the second component, and determine a second property evaluation corresponding to the second component, is the second component being associated with the first property evaluation.
    Type: Application
    Filed: September 26, 2013
    Publication date: May 8, 2014
    Applicant: Coverity, Inc.
    Inventors: Marat Boshernitsan, Andreas Kuehlmann, Scott McPeak, Philip Chong, Tobias Welp
  • Publication number: 20140096113
    Abstract: A method is provided to evaluate tests of computer program code comprising: configuring a computer to produce, in a computer readable storage device, a code filter to indicate one or more respective portions of the computer program code to respectively either omit from or to include in a determination of adequacy of results; and comparing test results with the computer program code with the one or more respective portions filtered using the code filter to respectively either omit the respective portions from or include the respective portions in the determination as indicated by the code filter.
    Type: Application
    Filed: March 15, 2013
    Publication date: April 3, 2014
    Inventors: Andreas Kuehlmann, Marat Boshernitsan
  • Patent number: 8656330
    Abstract: In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a solution. If the search finds a numeric assignment that satisfies each and every one of the one or more numeric formulas, it indicates that a functional property of the system is violated.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: February 18, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Andreas Kuehlmann, Kenneth L. McMillan, Shmuel Sagiv
  • Patent number: 8589845
    Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: November 19, 2013
    Inventors: Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone
  • Patent number: 8418101
    Abstract: Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machine in a sequence of time frames. At least one state is determined in a transition relation in the sequence that cannot be reached in a subsequent transition relation in the sequence. A subsequent transition relation in the sequence in which the at least one state cannot be reached is simplified with respect to the at least one unreachable state.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: April 9, 2013
    Assignee: Cadence Designs Systems, Inc.
    Inventors: Andreas Kuehlmann, Xiaoqun Du
  • Patent number: 8413090
    Abstract: Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machine in a sequence of time frames. At least one state is determined in a transition relation in the sequence that cannot be reached in a subsequent transition relation in the sequence. A subsequent transition relation in the sequence in which the at least one state cannot be reached is simplified with respect to the at least one unreachable state.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: April 2, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Andreas Kuehlmann, Xiaoqun Du
  • Patent number: 8307316
    Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: November 6, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone
  • Publication number: 20110252389
    Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to as certain sequential optimization based design flexibility throughout multiple stages of a design flow.
    Type: Application
    Filed: March 21, 2011
    Publication date: October 13, 2011
    Applicant: Cadence Design Systems, Inc.
    Inventors: Christoph ALBRECHT, Philip CHONG, Andreas KUEHLMANN, Ellen SENTOVICH, Roberto PASSERONE